64K x 16 1Mb Asynchronous SRAM
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1 TSOP, FP-BGA Commercial Temp Industrial Temp 64K x 16 1Mb Asynchronous SRAM GS71116AGP/U 7, 8, 10, 12 ns 3.3 V V DD Center V DD and V SS Features Fast access time: 7, 8, 10, 12 ns CMOS low power operation: 145/125/100/85 ma at minimum cycle time Single 3.3 V power supply All inputs and outputs are TTL-compatible Byte control Fully static operation Industrial Temperature Option: 40 to 85 C Package line up GP: RoHS-compliant 400 mil, 44-pin TSOP Type II package U: 6 mm x 8 mm Fine Pitch Ball Grid Array package GU: RoHS-compliant 6 mm x 8 mm Fine Pitch Ball Grid Array package Description The GS71116A is a high speed CMOS static RAM organized as 65,536-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. Operating on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS71116A is available in the 6 mm x 8 mm Fine Pitch BGA and 400 mil TSOP Type-II packages. Pin Descriptions Symbol A0 A15 DQ1 DQ16 LB UB WE OE V DD V SS NC Description Address input Data input/output Chip enable input Lower byte enable input (DQ1 to DQ8) Upper byte enable input (DQ9 to DQ16) Write enable input Output enable input +3.3 V power supply Ground No connect Fine Pitch BGA 64K x 16-Bump Configuration A LB OE A0 A1 A2 NC B DQ16 UB A3 A4 DQ1 C DQ14 DQ15 A5 A6 DQ2 DQ3 D V SS DQ13 NC A7 DQ4 V DD E V DD DQ12 NC NC DQ5 V SS F DQ11 DQ10 A8 A9 DQ7 DQ6 G DQ9 NC A10 A11 WE DQ8 H NC A12 A13 A14 A15 NC 6 mm x 8 mm, 0.75 mm Bump Pitch (Package U) Top View A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 DQ4 V DD V SS DQ5 DQ6 DQ7 DQ8 WE A15 A14 A13 A12 NC TSOP-II 64K x 16-Pin Configuration Top view 44-pin TSOP II A5 A6 A7 OE UB LB DQ16 DQ15 DQ14 DQ13 V SS V DD DQ12 DQ11 DQ10 DQ9 NC A8 A9 A10 A11 NC Package TP Rev: /2013 1/ , GSI Technology
2 Block Diagram A0 Address Input Buffer Row Decoder Memory Array A15 Column Decoder WE OE Control UB I/O Buffer DQ1 DQ16 Truth Table OE WE LB UB DQ1 to DQ8 DQ9 to DQ16 V DD Current H X X X X Not Selected Not Selected ISB1, ISB2 L L Read Read L L H L H Read High Z L X L H L High Z Read L L Write Write L H Write Not Write, High Z H L Not Write, High Z Write IDD L H H X X High Z High Z L X X H H High Z High Z Note: X: H or L Rev: /2013 2/ , GSI Technology
3 Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD 0.5 to +4.6 V Input Voltage VIN 0.5 to V DD +0.5 ( 4.6 V max.) V Output Voltage VOUT 0.5 to V DD +0.5 ( 4.6 V max.) V Allowable power dissipation PD 0.7 W Storage temperature TSTG 55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -7/-8/-10/-12 V DD V Input High Voltage VIH 2.0 V DD +0.3 V Input Low Voltage VIL V Ambient Temperature, Commercial Range Ambient Temperature, Industrial Range TAc 0 70 o C TAI o C Notes: 1. Input overshoot voltage should be less than V DD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than 2 V and not exceed 20 ns. Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN V IN = 0 V 5 pf Output Capacitance COUT V OUT = 0 V 7 pf Notes: 1. Tested at TA = 25 C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. Rev: /2013 3/ , GSI Technology
4 DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to V DD 1 ua 1uA Output Leakage Current ILO Output High Z VOUT = 0 to V DD 1 ua 1uA Output High Voltage VOH I OH = 4 ma 2.4 Output Low Voltage VOL I LO = +4 ma 0.4V Power Supply Currents Parameter Symbol Test Conditions 0 to 70 C 40 to 85 C 7 ns 8 ns 10 ns 12 ns 7 ns 8 ns 10 ns 12 ns Operating Supply Current IDD VIL All other inputs V IH or VIL Min. cycle time I OUT = 0 ma 145 ma 125 ma 100 ma 85 ma 150 ma 130 ma 105 ma 90 ma Standby Current ISB1 V IH All other inputs V IH or VIL Min. cycle time 25 ma 20 ma 20 ma 15 ma 30 ma 25 ma 25 ma 20 ma Standby Current ISB2 V DD 0.2 V All other inputs V DD 0.2 V or 0.2 V 2 ma 5 ma Rev: /2013 4/ , GSI Technology
5 AC Test Conditions Parameter Conditions DQ Output Load 1 Input high level VIH = 2.4 V Input low level VI L= 0.4 V 50Ω 30pF 1 Input rise time tr = 1V/ns VT = 1.4 V Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 589Ω Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output load 2 for tlz, thz, tolz and tohz 5pF 1 434Ω Rev: /2013 5/ , GSI Technology
6 AC Characteristics Read Cycle Parameter Symbol Min Max Min Max Min Max Min Max Unit Read cycle time trc ns Address access time taa ns Chip enable access time () tac ns Byte enable access time (UB, LB) tab ns Output enable to output valid (OE) toe ns Output hold from address change toh ns Chip enable to output in low Z () Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in High Z () t t t t LZ OLZ BLZ HZ * ns * ns * ns * ns Output disable to output in High Z (OE) t * ns OHZ Byte disable to output in High Z (UB, LB) t BHZ * * These parameters are sampled and are not 100% tested. Read Cycle 1: = OE = V IL, WE = V IH, UB and, or LB = V IL Address trc toh Data Out Previous Data Data valid taa Rev: /2013 6/ , GSI Technology
7 Read Cycle 2: WE = V IH trc Address taa UB, LB tlz tac tab thz OE tblz tbhz Data Out tolz High impedance toe tohz Data valid Write Cycle Parameter Symbol Min Max Min Max Min Max Min Max Unit Write cycle time twc ns Address valid to end of write taw ns Chip enable to end of write tcw ns Byte enable to end of write tbw ns Data set up time tdw ns Data hold time tdh ns Write pulse width twp ns Address set up time tas ns Write recovery time (WE) twr ns Write recovery time () twr ns Output Low Z from end of write twlz * ns Write to output in High Z twhz * ns * These parameters are sampled and are not 100% tested. Rev: /2013 7/ , GSI Technology
8 Write Cycle 1: WE control twc Address taw twr OE tcw tbw UB, LB WE tas twp Data In Data Out twhz tdw tdh Data valid twlz High impedance Write Cycle 2: control twc Address taw twr1 OE UB, LB tas tcw tbw WE twp Data In tdw Data valid tdh Data Out High impedance Rev: /2013 8/ , GSI Technology
9 Write Cycle 3: UB, LB control twc Address taw twr1 OE UB, LB tas tcw tbw WE twp Data In tdw Data valid tdh Data Out High impedance Rev: /2013 9/ , GSI Technology
10 44 Pin, 400 mil TSOP-II 44 D 23 c Dimension in inch Dimension in mm Symbol min nom max min nom max A A E HE A A B c e B D E e A A1 A2 y HE L L L1 L y Detail A Q Q 0 o 5 o 0 o 5 o Notes: 1. Dimension D& E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Controlling dimension: mm Rev: / / , GSI Technology
11 6 mm x 8 mm Fine Pitch BGA Bottom View pin A1 index 1.20(max) pin A1 index Top View ± 0.05 A B C D E F G H 0.75(typ). 0.36(typ) ± 0.10 D 6.00 ± 0.10 Ball Dia Pitch units: mm Rev: / / , GSI Technology
12 Ordering Information Part Number * Package Access Time Temp. Range GS71116AGP-7 RoHS-compliant 400 mil TSOP-II 7 ns Commercial GS71116AGP-8 RoHS-compliant 400 mil TSOP-II 8 ns Commercial GS71116AGP-10 RoHS-compliant 400 mil TSOP-II 10 ns Commercial GS71116AGP-12 RoHS-compliant 400 mil TSOP-II 12 ns Commercial GS71116AGP-7I RoHS-compliant 400 mil TSOP-II 7 ns Industrial GS71116AGP-8I RoHS-compliant 400 mil TSOP-II 8 ns Industrial GS71116AGP-10I RoHS-compliant 400 mil TSOP-II 10 ns Industrial GS71116AGP-12I RoHS-compliant 400 mil TSOP-II 12 ns Industrial GS71116AU-7 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71116AU-8 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71116AU-10 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71116AU-12 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71116AU-7I 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71116AU-8I 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71116AU-10I 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71116AU-12I 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial GS71116AGU-7 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 7 ns Commercial GS71116AGU-8 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 8 ns Commercial GS71116AGU-10 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 10 ns Commercial GS71116AGU-12 RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 12 ns Commercial GS71116AGU-7I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 7 ns Industrial GS71116AGU-8I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 8 ns Industrial GS71116AGU-10I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 10 ns Industrial GS71116AGU-12I RoHS-compliant 6 mm x 8 mm Fine Pitch BGA 12 ns Industrial Note: Customers requiring delivery in Tape and Reel should add the character T to the end of the part number. For example: GS71116AGP-8T. Rev: / / , GSI Technology
13 1Mb Asynchronous Datasheet Revision History Rev. Code: Old; New Types of Changes Format or Revision 71116A_r1 Creation of new datasheet 71116A_r1; 71116_r1_01 Added 6 ns speed bin to entire document 71116A_r1_01; 71116A _r1_ A_r1_02; 71116A _r1_ A_r1_03; 71116A _r1_ A_r1_04; 71116A _r1_ A_r1_05; 71116A_r1_ A_r1_06; 71116A_r1_ A_r1_07; 71116A_r1_ A_r1_08; 71116A_r1_ A_r1_09; 71116A_r1_10 /Format /Format Updated all power numbers Changed 6 mm x 10 mm FPBGA package designator from U to X Updated Recommended Operating Conditions table on page 4 Changed FPBGA package from 6 x 10 to 6 x 8 (package U) Updated Read Cycle AC Characteristics table Removed 6 ns speed bin from entire document Added 7 ns speed bin to entire document Updated timings for tbhz (Read Cycle) for 10 ns and 12 ns Updated format Added RoHS-compliant information for TSOP-II package Added RoHS-compliant information for FP-BGA package Added RoHS-compliant 400 mil SOJ Updated to MP in ordering information table Rev.1.09a Removed Status column from Ordering Information table. Removed reference to 400 mil, 44 pin SOJ package from entire document Removed 5/6-RoHS TSOP-II references due to EOL Rev: / / , GSI Technology
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2Mb Ultra-Low Power Asynchronous CMOS SRAM 128Kx16 bit Features Overview The is an integrated memory device containing a 2 Mbit Static Random Access Memory organized as 131,072 words by 16 bits. The device
MB85R K (32 K 8) Bit. Memory FRAM DS E CMOS DESCRIPTIONS FEATURES PACKAGES FUJITSU SEMICONDUCTOR DATA SHEET
FUJITSU SEMICONDUCTOR DATA SHEET DS05-13101-4E Memory FRAM CMOS 256 K (32 K 8) Bit MB85R256 DESCRIPTIONS The MB85R256 is an FRAM (Ferroelectric Random Access Memory) chip in a configuration of 32,768 words
1.8V Core Async/Page PSRAM
1.8V Core Async/Page PSRAM Overview The IS66WVE4M16ALL is an integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 4M words by 16 bits.
IS41C16257C IS41LV16257C
256Kx16 4Mb DRAM WITH FAST PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC standard
HIGH SPEED 128K (8K X 16 BIT) IDT70825S/L SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM )
HIGH SPEED 18K (8K X 16 BIT) SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM ) Features High-speed access Commercial: ///4 (max.) Low-power operation IDT78S Active: 77mW (typ.) Standby: mw (typ.) IDT78L
CAT28C17A 16K-Bit CMOS PARALLEL EEPROM
16K-Bit CMOS PARALLEL EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast Read Access Times: 200 ns Low Power CMOS Dissipation: Active: 25 ma Max. Standby: 100 µa Max. Simple Write Operation: On-Chip Address
My-MS. MM27C ,072 x 8 CMOS EPROM PRELIMINARY INFORMATION ISSI IS27C010 FEATURES DESCRIPTION FUNCTIONAL BLOCK DIAGRAM
IS27C010 ISSI MM27C010 131,072 x CMOS EPROM PRELIMINARY INFORMATION FEATURES Fast read access time: 90 ns JEDEC-approved pinout High-speed write programming Typically less than 16 seconds 5V ±10% power
CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
CMOS SyncFIFO 64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 IDT72420 IDT72200 IDT72210 IDT72220 IDT72230 IDT72240
A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16
64K x 16 Static RAM Features Pin- and function-compatible with CY7C1021BV33 High speed t AA = 8, 10, 12, and 15 ns CMOS for optimum speed/power Low active power 360 mw (max.) Data retention at 2.0V Automatic
1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018
1Mx16 16Mb DRAM WITH FAST PAGE MODE SEPTEMBER 2018 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden JEDEC
White Electronic Designs
12Kx32 EEPROM MODULE, SMD 5962-9455 FEATURES Access Times of 120**, 140, 150, 200, 250, 300ns Packaging: 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic Ceramic HIP (Package 400) 6 lead, 22.4mm sq.
WINTEC I. DESCRIPTION: III. TIMING
ISIONS ZONE DESCRIPTION APPVD 1/26/01 NR I. DESCRIPTION: III. TIMING is a 8Mx64 industry standard 8-pin PC-100 DIMM Manufactured with 4 8Mx 400-mil TSOPII-54 100MHz Synchronous DRAM devices Requires 3.3V+/-0.3V
MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION
![MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION](/thumbs/78/78720826.jpg "MX27C K-BIT [32K x 8] CMOS EPROM FEATURES GENERAL DESCRIPTION BLOCK DIAGRAM PIN CONFIGURATIONS PIN DESCRIPTION")
FEATURES 32K x 8 organization Single +5V power supply +125V programming voltage Fast access time: 45/55/70/90/100/120/150 ns Totally static operation Completely TTL compatible 256K-BIT [32K x 8] CMOS EPROM
AT24C01A/02/04/08/16. 2-Wire Serial CMOS E 2 PROM. Features. Description. Pin Configurations. 1K (128 x 8) 2K (256 x 8) 4K (512 x 8) 8K (1024 x 8)
AT24C01A/02/04/08/16 Features Low Voltage and Standard Voltage Operation 5.0 (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 2.5 (V CC = 2.5V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) Internally Organized 128
Industrial Temperature Range: -40 o C to +85 o C Lead-free available KEY TIMING PARAMETERS. Max. CAS Access Time (tcac) ns
1M x 16 (16-MBIT) DYNAMIC RAM WITH FAST PAGE MODE APRIL 2005 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: -Only, CAS-before- (CBR), and Hidden
8Mb Async/Page PSRAM
8Mb Async/Page PSRAM NOVEMBER 2015 Overview The IS66/67WVE51216EALL/BLL/CLL and IS66/67WVE51216TALL/BLL/CLL are integrated memory device containing 8Mbit Pseudo Static Random Access Memory using a self-refresh
CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,024 X 9, 2,048 X 9, 4,096 x 9 and 8,192 x 9
Integrated Device Technology, Inc. CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1,24 X 9, 2,48 X 9, 4,96 x 9 and 8,192 x 9 IDT72421 IDT7221 IDT72211 IDT72221 IDT72231 IDT72241 IDT72251 FEATURES: 64 x 9-bit
M8M644S3V9 M16M648S3V9. 8M, 16M x 64 SODIMM
MM644S3V9 MM64S3V9 SDRAM Features: JEDEC Standard 144-pin, PC100, PC133 small outline, dual in-line memory Module (SODIMM) Unbuffered TSOP components. Single 3.3v +.3v power supply. Fully synchronous;
CAT28C K-Bit Parallel EEPROM
256K-Bit Parallel EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast read access times: 120/150ns Low power CMOS dissipation: Active: 25 ma max Standby: 150 µa max Simple write operation: On-chip address and
IS41C16256C IS41LV16256C
256Kx16 4Mb DRAM WITH EDO PAGE MODE JANUARY 2013 FEATURES TTL compatible inputs and outputs; tri-state I/O Refresh Interval: 512 cycles/8 ms Refresh Mode : -Only, CAS-before- (CBR), and Hidden JEDEC standard
MOS INTEGRATED CIRCUIT
DATA SHEET MOS INTEGRATED CIRCUIT µpd42s18165, 4218165 16 M-BIT DYNAMIC RAM 1 M-WORD BY 16-BIT, HYPER PAGE MODE, BYTE READ/WRITE MODE Description The µpd42s18165, 4218165 are 1,048,576 words by 16 bits
ACT-S128K32 High Speed 4 Megabit SRAM Multichip Module
CT-S128K32 High Speed 4 Megabit SRM Multichip Module Features 4 Low Power CMOS 128K x 8 SRMs in one MCM Overall configuration as 128K x 32 Input and Output TTL Compatible 17, 20, 25, 35, 45 & 55ns ccess
IS62/65WVS1288FALL IS62/65WVS1288FBLL. 128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE DESCRIPTION
128Kx8 LOW VOLTAGE, SERIAL SRAM with SPI, SDI and SQI INTERFACE JANUARY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 16/20 MHz Clock rate - SPI/SDI/SQI mode Low-Power CMOS Technology: - Read Current:
MX23L M-BIT MASK ROM (8/16-BIT OUTPUT) FEATURES PIN CONFIGURATION PIN DESCRIPTION 44 SOP ORDER INFORMATION
32M-BIT MASK ROM (8/16-BIT OUTPUT) FEATURES Bit organization - 4M x 8 (byte mode) - 2M x 16 (word mode) Fast access time - Random access: 70ns (max.) - Page access: 25ns (max.) Page Size - 8 words per
512KX8 CMOS S-RAM (Monolithic)
512KX8 CMOS S-RAM (Monolithic) Features Access Times: 55, 70, 85 and 100ns Package Option: 32-Pin Ceramic DIP, JEDEC Approved Pinout 36-Lead Ceramic SOJ JEDEC Approved Revolutionary Pinout 32-Lead Ceramic
Am27C020. Advanced Micro Devices. 2 Megabit (262,144 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 2 Megabit (262,144 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 70 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved pinout Plug
Product Specifications
Product Specificatio L75S655BGAS. General Information 5MB 6Mx7 SDRAM PC ECC REGISTERED PIN SODIMM Description: The L75S655B is a 6Mx 7 Synchronous Dynamic RAM high deity memory module. This memory module
Am27C512. Advanced Micro Devices. 512 Kilobit (65,536 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 512 Kilobit (65,536 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 55 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
DS1249Y/AB 2048k Nonvolatile SRAM
19-5631; Rev 11/10 www.maxim-ic.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Unlimited write cycles Low-power CMOS operation
IS41C16100C IS41LV16100C
1Mx16 16Mb DRAM WITH EDO PAGE MODE FEBRUARY 2012 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR), and Hidden Self
High Performance 4Kx4 Static RAM MIL-STD-883C
High Performance 4Kx4 Static RAM MIL-STD-883C FEATURES Full Military Temperature Operating Range (-55 0 C to + 125 0 C) MIL-STD-883C Processing 4Kx4 Bit Organisation 55 and 70 nsec-agce-ss-times Fully
IS62/65WVS5128GALL IS62/65WVS5128GBLL. 512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION
512Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE JUNE 2018 KEY FEATURES SPI-Compatible Bus Interface: - 30/45 MHz Clock rate - SPI/SDI/SQI mode Single Power Supply: - VDD = 1.65V -
Am27C128. Advanced Micro Devices. 128 Kilobit (16,384 x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM FINAL
FINAL 128 Kilobit (16,384 x 8-Bit) CMOS EPROM Advanced Micro Devices DISTINCTIVE CHARACTERISTICS Fast access time 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout Single
HIGH-SPEED 4K x 8 FourPort TM STATIC RAM
Features High-speed access Commercial: // (max.) Industrial: (max.) ow-power operation IDT754 Active: 75mW (typ.) tandby: 7.5mW (typ.) IDT754 Active: 75mW (typ.) tandby: mw (typ.) True FourPort memory
IS62/65WVS1288GALL IS62/65WVS1288GBLL. 128Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE KEY FEATURES DESCRIPTION MAY 2018
128Kx8 LOW VOLTAGE, FAST SERIAL SRAM with SPI, SDI and SQI INTERFACE MAY 2018 KEY FEATURES SPI-Compatible Bus Interface: - 30/45 MHz Clock rate - SPI/SDI/SQI mode Single Power Supply: - VDD = 1.65V - 2.2V
P2M648YL, P4M6416YL. PIN ASSIGNMENT (Front View) 168-PIN DIMM. 8-2Mx8 SDRAM TSOP P2M648YL-XX 16-2Mx8 SDRAM TSOP P4M6416YL-XX
SDRAM MODULE Features: JEDEC - Standard 168-pin (gold), dual in-line memory module (DIMM). TSOP components. Single 3.3v +.3v power supply. Nonbuffered fully synchronous; all signals measured on positive
ICE27C Megabit(128KX8) OTP EPROM
1- Megabit(128KX8) OTP EPROM Description The is a low-power, high-performance 1M(1,048,576) bit one-time programmable read only memory (OTP EPROM) organized as 128K by 8 bits. It is single 5V power supply
P8M644YA9, 16M648YA9. PIN ASSIGNMENT (Front View) 168-PIN DIMM. 4-8Mx16 SDRAM TSOP P8M644YA9 8-8Mx16 SDRAM TSOP P16M648YA9
SDRAM MODULE P8M644YA9, 16M648YA9 8M, 16M x 64 DIMM Features: PC100 and PC133 - compatible JEDEC - Standard 168-pin, dual in-line memory module (DIMM). TSOP components. Single 3.3v +. 3v power supply.
GND I/O15 I/O14 I/O13 I/O12 GND I/O11 I/O10 I/O9 I/O8 LCAS UCAS OE A9 A8 A7 A6 A5 A4 GND
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE DECEMBER 2006 FEATURES TTL compatible inputs and outputs; tristate I/O Refresh Interval: Auto refresh Mode: 1,024 cycles /16 ms -Only, CAS-before- (CBR),
D0 - D8 INPUT REGISTER. RAM ARRAY 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 OUTPUT REGISTER RESET LOGIC RCLK REN1
CMOS SyncFIFO 64 x 9, 256 x 9, 512 x 9, 1,24 x 9, 2,48 x 9, 4,96 x 9 and 8,192 x 9 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 218 FEATURES: 64 x 9-bit organization (IDT72421)