ELCT 501: Digital System Design

Transcription

1 ELCT 501: Digital System Lecture 3: Memory and Programmable Logic (continue) Dr. Mohamed Abd El Ghany,

2 Memory Model 32-bit address space can address up to 4 GB (2 32 ) different memory locations 0x x x x0A 0xB6 0x41 Lower Memory Address 0x xFC 0xFFFFFFFF Higher Memory 0x0D Address Flat Memory Model 2

3 Endianness [Danny Cohen 91] A byte ordering- How a multiple byte data word stored in memory Endianness (from Gulliver s Travels) Big Endian Most significant byte of a multi-byte word is stored at the lowest memory address E.g. Sun Sparc, PowerPC Little Endian Least significant byte of a multi-byte word is stored at the lowest memory address e.g. Intel x86 Some embedded & DSP processors would support both for interoperability 3

4 Endianness Examples Store 0x at address 0x0000 0x0000 0x0001 0x0002 0x87 0x65 0x43 Lower Memory Address 0x0000 0x0001 0x0002 0x21 0x43 0x65 Lower Memory Address 0x0003 0x21 0x0003 0x87 LITTLE ENDIAN Higher Memory Address BIG ENDIAN Higher Memory Address 4

5 Read Only Memory (ROM) Permanent binary information is stored Non-volatile memory Power off does not erase information stored K-bit address lines K ROM 2 k words N-bit per work N-bit Data Output N 5

6 32x8 ROM A4 A3 A2 A1 A0 5-to-32 Decoder x8 ROM 8 Each represents 32 wires Fuse can be implemented as a diode or a pass transistor D7 D6 D5 D4 D3 D2 D1 D0 6

7 Programming the 32x8 ROM A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D A4 A3 A2 A1 A0 5-to-32 Decoder D7 D6 D5 D4 D3 D2 D1 D0 7

8 Example: Lookup Table a square lookup table for F(X)=X 2 using ROM X F(X)=X X F(X)=X

9 Square Lookup Table using ROM X F(X)=X X2 X1 X to Decoder F5 F4 F3 F2 F1 F0 9

10 Square Lookup Table using ROM X F(X)=X X2 X1 X to Decoder F5 F4 F3 F2 F1 F0 Not used =X0 10

11 Square Lookup Table using ROM X F(X)=X X2 X1 X to Decoder F5 F4 F3 F2 F1 F0 11

12 Classifying Three Basic PLDs INPUT INPUT Fixed AND plane (decoder) Programmable AND plane Programmable Connections Programmable OR plane (Programmable) Read-Only Memory (ROM) Programmable Connections Programmable Logic Array (PLA) Programmable OR plane OUTPUT OUTPUT INPUT Programmable AND plane Fixed OR plane Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD s lawyers F/F OUTPUT 12

13 Programmable Logic Array (PLA) A B Programmable OR Plane C Programmable AND Plane C C B B A A F2 13

14 Example using PLA F1(A,B, C) m(0,1,2,4) F2(A,B, C) m(0,5,6,7) F1 AB AC BC F1 AB AC BC F2 AB AC ABC 14

15 Example using PLA A B C C C B B A A F1 AB AC F2 AB AC BC ABC AB AC BC A B C F1 F2 15

16 PAL Device A A B B IO2 IO2 IO1 IO1 Programmable AND Plane A IO1 IO2 B Fixed OR Plane 16

17 PAL Device Example A A B B C C D D IO1 IO1 IO1 A Not programmed IO2 B IO1 ABC ABCD IO2 ABC ABCD ACD ABCD 17

18 CPLD and FPGA [brown & Rose 96] Complex Programmable Logic Device (CPLD) Multiple PLDs (e.g. PALs, PLAs) with Programmable interconnection structure Pioneered by Altera Field-Programmable Gate Array (FPGA) High logic capacity with large distributed interconnection structure Logic capacity= number of 2-input NAND gates Offers more narrow logic resources CPLD offers logic resources with a wide number of inputs (AND planes) Offer a higher ratio of Flip-flops to logic resources than CPLD High Capacity PLD (HCPLD) is often used to refer to both CPLD and FPGA 18

19 CPLD Structure Logic block PLD PLD PLD PLD I/O block Interconnects PLD PLD PLD PLD 19

20 FPGA Structure Logic block I/O block Interconnects 20

21 FPGA Programmability Floating gate transistor Used in EPROM and EEPROM SRAM-controlled switch-control Pass transistors Multiplexers (to determine how to route inputs) Antifuse Similar to fuse Originally an Open-Circuit One-Time Programmable (OTP) 21

22 References Logic and Computer Fundamentals by M. Morris Mano and Charles R. Kime. 4th edition, Prentice Hall P. Marwedel: Embedded System, Springer, 2006 First Steps with Embedded Systems Byte Craft Limited 22