512Mb NAND FLASH + 256Mb LPDDR SDRAM MCP Product
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1 Multi-Chip Package MEMORY 512M bit(1.8v,32m x 16) 256M bit(1.8v,16m x 16) SLC NAND Flash LPDDR(Mobile DDR) SDRAM Revision No. History Draft Date Remark 00 Initial Draft Nov
2 Multi-Chip Package MEMORY 512M bit (x16,1.8v) NAND Flash and 256M bit (x16,1.8v) LPDDR SDRAM <MCP Features>. Operating Temperature : -25 ~ ball FBGA Type 8.0mmx9.0mm <NAND Features> Power Supply -1.8V Device : 1.7V ~ 1.95V Organization -Memory Cell Array : (32M + 1M) x 16bits -Data Register : ( ) x 16bits Automatic Program and Erase -Page Program : ( ) words -Block Erase : (8K +256) words Page Read Operation -Page Size : ( ) words -Random Access : 15us(Max.) -Serial Page Access : 50ns(Min.) Fast Write Cycle Time -Program time : 200us(Typ.) -Block Erase time : 2ms(Typ.) Copy-Back PROGRAM Operation -Fast Page copy without external buffering Command Register Operation Security features -OTP area, 8K words (32 pages) Hardware Data Protection -Program / Erase locked during Power transitions Data Integrity -Endurance : 100K Program / Erase Cycles (With 1bit/264 words ECC) -Data Retention : 10 years <LPDDR SDRAM Features> Density: 256 Mbits Organization 4Meg 4banks 16bits Power supply: - VDD / VDDQ = 1.7V ~ 1.95V Data rate: 333Mbps (max) Differential clock inputs (CK and /CK) Bidirectional data strobe per byte of data Commands entered on each positive CK edge DQS edge-aligned with data for READs; centeraligned with data for WRITEs Four internal banks for concurrent operation Data mask (DM) for write data one mask per byte Programmable Burst Lengths: 2, 4,8 or 16 Burst type: Sequential or interleave Clock Stop capability Concurrent Auto Precharge option is supported Configurable Drive Strength (DS) Auto Refresh and Self Refresh Modes Optional Partial Array Self Refresh (PASR) and Temperature Compensated Self Refresh (TCSR) Deep Power Down Mode (DPD) 1.8V LVCMOS-compatible inputs Status Read Register (SRR) 64ms refresh 2
3 MCP Product Information Part number NAND Flash LPDDR SDRAM Package MST9B16B16FMHC-533E 512Mbit (x16) 1.8V 256Mbit (x16) 1.8V FBGA 130 ball 3
4 PIN CONFIGURATION(130-FBGA) A NC NC RE# CLE VCCn CE# WEn# VDD VSS NC A B VSS A4 WP# ALE VSSn R/B# DQ15 DQ14 VDDQ VSSQ B C VDD A5 A7 A9 DQ9 DQ11 DQ13 DQ12 VSSQ VDDQ C D A6 A8 CKE NC UDQS NC UDQM DQ10 VDDQ VSSQ D E A12 A11 NC NC NC DQ8 NC NC VSSQ VDDQ E F NC RAS# NC NC NC NC NC CLK VDDQ VSSQ F G VDD CAS# NC NC NC NC NC CLK# VSS VDD G H VSS CS# BA0 NC NC NC LDQS LDQM VSSQ VDDQ H I WE# BA1 A10 A0 DQ7 NC DQ6 DQ4 VDDQ VSSQ I J A1 A2 A3 DQ0 DQ1 DQ2 DQ3 DQ5 VDDQ VSSQ J K VDD VSS NC NC IO3 IO5 IO14 IO7 VSSQ VDDQ K L IO0 IO1 IO2 IO10 VCCn IO6 IO13 IO15 VDDQ VSSQ L M NC IO8 IO9 IO11 IO12 VSSn IO4 VDD VSS NC M NC NAND Mo-DDR 4
5 PIN DESCRIPTION -130-FBGA 512Mb(32Mb x 16) NAND Flash SYMBOL DESCRIPTION IO0~IO15 Data Input / Output CE# Chip Enable WEn# Write Enable RE# Read Enable ALE Address Latch Enable CLE Command Latch Enable WP# Write Protect R/B# Ready/Busy out VCCn Power Supply VSSn Ground 256Mb(16Mb x 16) LPDDR SYMBOL A0~A12 BA0, BA1 DQ0~DQ15 CS# RAS# CAS# WE# LDQM/UDQM LDQS/UDQS CLK,CLK# CKE VDD VDDQ VSS VSSQ Common SYMBOL NC DESCRIPTION Address Inputs Bank Address Inputs Data Bus Chip Select Row Address Strobe Command Column Address Strobe Command Write Enable Input Data Mask Data Strobe Clock Input Clock Enable Power Supply I/O Power supply Ground I/O Ground DESCRIPTION No Connection 5
6 FBGA 130 Ball 8 9 mm - package outline -1 6
7 FBGA 130 Ball 8 9 mm - package outline -2 NOTE : 1. All dimensions are in millimeters 2. Post reflow solder all diameter. (Pre reflow diameter : 0.40±0.02) 3. Tolerance Includes warpage. 7
8 Ordering Information MST 9 X XX X XX X X XX - X XXXX Customer code ATO Solution Co. Ltd Temperature Range E : -25 C ~ 85 C Product type 9 : NAND Flash + LPDDR SDRAM LPDDR SDRAM speed 33 : 333Mbps NAND Flash Density B : 512Mbit NAND Flash speed 5 : 50ns NAND Flash I/O 16 : x16 Package HF: 130-ball FBGA LPDDR SDRAM Density B : 256Mbit Generation M : 1 st Generation LPDDR SDRAM I/O 16 : x16 Voltage F : NAND Flash 1.8V, LPDDR SDRAM 1.8V 8
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