UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater Data Sheet August, 2002
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1 Standard Products UT54LVDM328 Octal 400 Mbps Bus LVDS Repeater Data Sheet August, 2002 FEATURES Mbps low jitter fully differential data path 200MHz clock channel 3.3 V power supply 10mA LVDS output drivers Cold sparing all pins Fast propagation delay of 3.5ns max Receiver input threshold < mv Radiationhardened design; total dose irradiation testing to MILSTD883 Method 1019 Totaldose: 300 krad(si) and 1 Mrad(Si) Latchup immune (LET > 100 MeVcm 2 /mg) Packaging options: 48lead flatpack Standard Microcircuit Drawing QML Q and V compliant part Compatible with ANSI/TIA/EIA LVDS Standard INTRODUCTION The UT54LVDM328 is an Octal Bus Repeater utilizing Low Voltage Differential Signaling (LVDS) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. LVDS I/O enable high speed data transmission for pointto point or multidrop interconnects. This device is designed for use as a high speed differential repeater. The UT54LVDM328 is a repeater designed specifically for the bridging of multiple backplanes in a system. The UT54LVDM328 utilizes low voltage differential signaling to deliver high speed while consuming minimal power with reduced EMI. The UT54LVDM328 repeats signals between backplanes and accepts or drives signals onto the local bus. The individual LVDS outputs can be put into TriState by use of the enable pins. All pins have Cold Spare buffers. These buffers will be high impedance when V DD is tied to V SS. END IN1+ + IN1 OUT2 IN2+ + IN2 OUT2+ OUT1+ OUT1 Figure 1a. UT54LVDM328 Repeater Block Diagram (Partial see Page 2 for complete diagram) 1
2 END IN1+ + IN1 OUT2+ IN3+ + IN3 OUT4+ IN5+ + IN5 IN6+ + OUT6+ IN7+ + IN7 OUT8+ OUT8 Clk Out+ Clk Out IN8+ + IN8 ENCK Clk In+ Clk In + OUT1+ OUT1 OUT2 IN2+ + IN2 OUT3+ OUT3 OUT4 IN4+ + IN4 OUT5+ OUT5 OUT6 IN6 OUT7+ OUT7 Figure 1b. UT54LVDM328 Repeater Diagram 2
3 IN1+ IN2+ VDD VSS IN3+ IN3 IN4+ ENCK CLK In+ END IN5+ IN6+ VDD VSS IN7+ IN8+ CLK In IN5 IN6 IN UT54LVDM328 Bus Repeater Figure 2. UT54LVDM328 Pinout OUT1+ OUT2+ VDD VSS OUT3+ OUT4+ VDD CLK OUT+ VSS OUT5+ CLK OUT OUT5 OUT6+ VDD VSS 25 OUT8 IN1 IN2 IN4 IN7 OUT1 OUT2 OUT3 OUT4 OUT6 OUT7+ OUT7 OUT8+ PIN DESCRIPTION Name # of Pins Description INn+ 8 Noninverting LVDS input INn 8 Inverting LVDS input OUTn+ 8 Noninverting LVDS output OUTn 8 Inverting LVDS Output END 1 A logic low on the enable puts the LVDS data output into Tri State and reduces the supply current ENCK 1 A logic low on the enable puts the LVDS clock output into Tri State and reduces the supply current V SS 5 Ground V DD 5 Power supply CLK IN+ 1 NonInverting Clock LVDS Input CLK IN 1 Inverting clock LVDS Input CLK OUT+ CLK OUT 1 NonInverting Clock LVDS Output 1 Inverting Clock LVDS Output 3
4 APPLICATIONS INFORMATION The UT54LVDM328 provides the basic bus repeater function. The device operates as a 9 channel LVDS buffer. Repeating the signal restores the LVDS amplitude, allowing it to drive another media segment. This allows for isolation of segments or long distance applications. The intended application of these devices and signaling technique is for both pointtopoint baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printedcircuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics.) Input FailSafe: The UT54LVDM328 also supports OPEN, shorted and terminated input failsafe. Receiver output will be HIGH for all failsafe conditions. PCB layout and Power System Bypass: Circuit board layout and stackup for the UT54LVDM328 should be designed to provide noisefree power to the device. Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which improves power supply filtering, especially at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range 0.01µF to 0.1µ F. Tantalum capacitors may be in the range of 2.2µF to 10µF. Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used. It is recommended practice to use two vias at each power pin of the UT54LVDM328, as well as all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance and extends the effective frequency range of the bypass components. The outer layers of the PCB may be flooded with additional ground plane. These planes will improve shielding and isolation, as well as increase the intrinsic capacitance of the power supply plane system. Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with vias. Frequent via placement also improves signal integrity in signal transmission lines by providing short paths for image currents which reduces signal distortion. The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line from the internal power or ground plane(s) whichever is greater. Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads. Compatibility with LVDS standard: In backplane multidrop configurations, with closely spaced loads, the effective differential impedance of the line is reduced. If the mainline has been designed for 50Ω differential impedance, the loading effects may reduce this to the 35Ω range depending upon spacing and capacitance load. Terminating the line with a 35Ω load is a better match than with 50Ω and reflections are reduced. 4
5 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to V SS ) SYMBOL PARAMETER LIMITS V DD DC supply voltage 0.3 to 4.0V V I/O Voltage on any pin 0.3 to (V DD + 0.3V) T STG Storage temperature 65 to +150 C P D Maximum power dissipation 800mW T J Maximum junction temperature C Θ JC Thermal resistance, junctiontocase 3 22 C/W I I DC input current ±10mA Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175 C during burnin and life test. 3. Test per MILSTD883, Method For cold spare mode (V DD = V SS ), V I/O may be 0.3V to the maximum recommended operating V DD +0.3V. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS V DD Positive supply voltage 3.3 to 3.6V T C Case temperature range 55 to +125 C V IN DC input voltage, receiver inputs 0 to 2.4V DC input voltage, logic inputs 0 to V DD for END or ENCK 5
6 DC ELECTRICAL CHARACTERISTICS 1 (V DD = 3.3V + 0.3V; 55 C < T C < +125 C) SYMBOL PARAMETER CONDITION MIN MAX UNIT CMOS/TTL DC SPECIFICATIONS (EN) V IH Highlevel input voltage 2.0 V DD V V IL Lowlevel input voltage GND 0.8 V I IH Highlevel input current V IN =3.6V; V DD = 3.6V µa I IL Lowlevel input current V IN =0V; V DD = 3.6V µa V CL Input clamp voltage I CL =18mA 1.5 V I CS Cold Spare Leakage current V IN =3.6V, V DD =V SS µα LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT) V OD Differential Output Voltage R L = 35Ω (See Figure 9) mv V OD Change in V OD between complimentary output states R L = 35Ω (See Figure 9) 35 mv V OS Offset Voltage R L = 35Ω V OS =(V OH +V OL ) V 2 V OS Change in V OS between complimentary output states R L =35Ω 35 mv I OZ Output TriState Current TriState output, V DD = 3.6V V OUT =V DD or GND +10 µα I CSOUT Cold Sparing Leakage Current V OUT =3.6V, V DD =V SS µα 2,3 I OS Output Short Circuit Current V OUT + OR V OUT = 0 V 25 ma LVDS RECEIVER DC SPECIFICATIONS (IN+, IN) V 3 TH Differential Input High Threshold V CM = +1.2V +100 mv V 3 TL Differential Input Low Threshold V CM = +1.2V 100 mv V CMR Common Mode Voltage Range V ID =210mV V I IN Input Current V IN = +2.4V, V DD = 3.6V µα V IN = 0V, V DD = 3.6V µα I CSIN Cold Sparing Leakage Current V IN =3.6V, V DD =V SS µα 6
7 DC ELECTRICAL CHARACTERISTICS 1 (CON"T) SYMBOL PARAMETER CONDITION MIN MAX UNIT Supply Current I CCL Total Supply Current R L = 35Ω END, ENCK= V DD, V DD = 3.6V 220 ma ICCZ TriState Supply Current END, ENCK = V SS, V DD = 3.6V 20 ma Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground. 2. Output short circuit current (I OS ) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. 3. Guaranteed by characterization. 7
8 AC SWITCHING CHARACTERISTICS (V DD = +3.3V + 0.3V, T A = 55 C to +125 C) SYMBOL PARAMETER Conditions MIN MAX UNIT t PHZ 2 t PLZ 2 t PZH 2 t PZL 2 Disable Time (Active to TriState) High to Z (See Figure 7) Disable Time (Active to TriState) Low to Z (See Figure 7) Enable Time (TriState to Active) Z to High (See Figure 7) Enable Time (TriState to Active) Z to Low (See Figure 7) t LHT 1 Output LowtoHigh Transition Time, 20% to 80% (See Figures 4 and 5) t HLT 1 Output HightoLow Transition Time, 80% to 20% (See Figures 4 and 5) t PLHD T PHLD T SKEW T CCS Propagation Low to High Delay (See Figures 4 and 6) Propagation High to Low Delay (See Figures 4 and 6) Differential Skew T PHLD T PLHD (See Figures 4 and 6) Output ChanneltoChannel Skew (See Figures 4 and 6) R L = 35Ω, C L = 10pf 4.5 ns R L = 35Ω, C L = 10pf 4.5 ns R L = 35Ω, C L = 10pf 11.0 ns R L = 35Ω, C L = 10pf 11.0 ns R L = 35Ω, C L = 10pf 600 ps R L = 35Ω, C L = 10pf 600 ps R L = 35Ω, C L = 10pf 3.5 ns R L = 35Ω, C L = 10pf 3.5 ns 900 ps 500 ps Notes: 1. Guaranteed by design. 2. Guaranteed by characterization.. 8
9 R IN+ C L Pulse Generator R IN R D RL 50Ω 50Ω C L Figure 4. LVDS Output Load 80% 80% V DIFF 0V 20% 20% t LHT t HLT Figure 5. LVDS Output Transition Time IN Vdiff = 0V t PLHD t PHLD OUT Vdiff = 0V Figure 6. Propagation Delay LowtoHigh and HightoLow 9
10 EN V DD V DD/2 V DD/2 OUT t PHZ t PZH V OH 50% 50% 0VDiff 0VDiff 50% 50% OUT V OL t PLZ t PZL Figure 7. Output active to TRISTATE and TRISTATE to active OUT 0 Vdiff = 0V TCCS OUT 1 Vdiff = 0V Figure 8. Output ChanneltoChannel Skew D OUT+ D IN 20pF Generator D R L = 35Ω V OD 50Ω Driver Enabled 20pF D OUT Figure 9. Driver V OD and V OS Test Circuit or Equivalent Circuit 10
11 PACKAGING Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MILPRF The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MILPRF Package dimensions and symbols are similar to MILSTD1835 Requirement 101, Configuration B. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option. 7. With solder, increase maximum by Figure pin Flatpack 11
12 ORDERING INFORMATION UT54LVDM328 Bus LVDS Repeater: UT 54LVDM328 * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (U) = 48lead Flatpack (dualinline) Access Time: Not applicable Device Type: UT54LVDM328 Bus LVDS Repeater Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an X is specified when ordering, then the part marking will match the lead finish and will be either A (solder) or C (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25 C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at 55 C, room temp, and 125 C. Radiation neither tested nor guaranteed. 12
13 UT54LVDM328 Bus LVDS Repeater: SMD ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (Y) = 48lead Flatpack (dualinline) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = Bus LVDS Repeater Drawing Number: Total Dose (R) = 1E5 rad(si) (F) = 3E5 rad(si) (G) = 5E5 rad(si) (H) = 1E6 rad(si) Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an X is specified when ordering, part marking will match the lead finish and will be either A (solder) or C (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 13
14 NOTES 14
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