EVALUATION KIT AVAILABLE Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs. S Inputs. S Outputs

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1 19-491; Rev ; 1/9 EVALUATION KIT AVAILABLE General Description The is a highly flexible, precision phaselocked loop (PLL) clock generator optimized for the next generation of network equipment that demands low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power-supply noise rejection, and pin-programmable LVDS/ output interfaces. The provides nine differential outputs and one output, divided into three banks. The frequency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space. This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -4 C to +85 C. Ethernet Switch/Router Wireless Base Station Applications PCIeM, Network Processors DDR/QDR Memory Typical Application Circuits and Pin Configuration appear at end of data sheet. S Inputs Crystal Interface: 18MHz to 33.5MHz Input: 15MHz to 16MHz Differential Input: 15MHz to 35MHz S Outputs Output: Up to 16MHz /LVDS Outputs: Up to 8MHz S Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable Output Interface Features S Wide VCO Tuning Range (3.83GHz to 4.25GHz) S Low Phase Jitter.34psRMS (12kHz to 2MHz).14psRMS (1.875MHz to 2MHz) S Excellent Power-Supply Noise Rejection S -4 to +85 Operating Temperature Range S Supply Ordering Information PART TEMP RANGE PIN-PACKAGE ETM+ -4 to TQFN-EP* +Denotes a lead(pb)-free/rohs-compliant package. *EP = Exposed pad. Functional Diagram /LVDS QA QA /LVDS QA1 QA1 /LVDS QA2 QA2 XOUT XO /LVDS QA3 QA3 XIN /LVDS QA4 PLL, DIVIDERS, MUXES QA4 CIN VCO /LVDS QB QB /LVDS QB1 QB1 /LVDS QB2 QB2 /LVDS QC QC QCC PCIe is a registered trademark of PCI-SIG Corp. Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS Supply Voltage Range (V CC, V CCA, V CCQA, V CCQB, V CCQC, V CCQCC )...-.3V to +4.V Voltage Range at CIN, IN_SEL, DM, DF[1:], DP, PLL_BP, DA[1:], DB[1:], DC[1:], QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL, QCC, RES V to (V CC +.3V) Voltage Range at,... (V CC V) to (V CC -.35V) Voltage Range at QA[4:], QA[4:], QB[2:], QB[2:], QC, QC when LVDS Output V to (V CC +.3V) Current into QA[4:], QA[4:], QB[2:], QB[2:], QC, QC when Output mA Current into QCC... Q5mA Voltage Range at XIN...-.3V to +1.2V Voltage Range at XOUT...-.3V to (V CC -.6V) Continuous Power Dissipation (T A = +7) 48-Pin TQFN (derate 4mW/ above +7)...32mW Operating Junction Temperature Range to +15 Storage Temperature Range to +16 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V CC = +3.V to +3.6V, T A = -4 C to +85 C. Typical values are at V CC =, T A = +25 C, unless otherwise noted. Signal applied to CIN or / only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current with PLL Enabled (Note 2) Supply Current with PLL Bypassed (Note 2) Configured with outputs I CC Configured with LVDS outputs Configured with outputs 11 Configured with LVDS outputs 23 /LVTTL CONTROL INPUTS (IN_SEL, DM, DF[1:], DA[1:], DB[1:], DC[1:], PLL_BP, DP, QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL) Input High Voltage V IH 2. V Input Low Voltage V IL.8 V Input High Current I IH V IN = V CC 8 FA Input Low Current I IL V IN = V -8 FA /LVTTL CLOCK INPUT (CIN) Reference Clock Input Frequency f REF MHz Input Amplitude Range Internally AC-coupled (Note 3) V P-P Input High Current I IH V IN = V CC 8 FA Input Low Current I IL V IN = V -8 FA Reference Clock Input Duty- Cycle Distortion ma ma 4 6 % Input Capacitance 1.5 pf DIFFERENTIAL CLOCK INPUT (, ) (Note 4) Differential Input Frequency f REF MHz Input Bias Voltage V CMI V CC Input Differential Voltage Swing mv P-P Single-Ended Voltage Range Input Differential Impedance I Differential Input Capacitance 1.5 pf V CC - 2. V CC V CC -.7 V V 2

3 ELECTRICAL CHARACTERISTICS (continued) (V CC = +3.V to +3.6V, T A = -4 C to +85 C. Typical values are at V CC =, T A = +25 C, unless otherwise noted. Signal applied to CIN or / only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS OUTPUTS (QA[4:], QA[4:], QB[2:], QB[2:], QC, QC) (Note 5) Output Frequency 8 MHz Output High Voltage V OH V Output Low Voltage V OL.925 V Differential Output Voltage V OD 25 4 mv Change in Magnitude of Differential Output for Complementary States D V OD 25 mv Output Offset Voltage V OS V Change in Magnitude of Output Offset Voltage for Complementary States D V OS 25 mv Differential Output Impedance I Output Current Short together 3 Short to ground 6 Output Current When Disabled V Q = V Q = V to V CC 1 FA Output Rise/Fall Time 2% to 8% ps Output Duty-Cycle Distortion PLL enabled PLL bypassed (Note 6) 5 OUTPUTS (QA[4:], QA[4:], QB[2:], QB[2:], QC, QC) (Note 7) Output Frequency 8 MHz Output High Voltage V OH V CC Output Low Voltage V OL V CC Output-Voltage Swing (Single-Ended) V CC -.98 V CC V CC -.83 V CC ma % V P-P Output Current When Disabled V O = V to V CC 1 FA Output Rise/Fall Time 2% to 8%, differential load = 1I ps Output Duty-Cycle Distortion /LVTTL OUTPUT (QCC) PLL enabled PLL bypassed (Note 6) 5 Output Frequency 16 MHz Output High Voltage I OH = -12mA 2.6 V CC V Output Low Voltage I OL = 12mA.4 V Output Rise/Fall Time 2% to 8% (Note 8) ps Output Duty-Cycle Distortion PLL enabled PLL bypassed (Note 6) 5 Output Impedance 15 I V V % % 3

4 ELECTRICAL CHARACTERISTICS (continued) (V CC = +3.V to +3.6V, T A = -4 C to +85 C. Typical values are at V CC =, T A = +25 C, unless otherwise noted. Signal applied to CIN or / only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PLL SPECIFICATIONS VCO Frequency Range f VCO MHz Phase-Frequency Detector Compare Frequency f PFD MHz PLL Jitter Transfer Bandwidth 13 khz Integrated Phase Jitter Supply-Noise Induced Phase Spur at /LVDS Output Supply-Noise Induced Phase Spur at Output Determinisitic Jitter Induced by Power-Supply Noise Nonharmonic and Subharmonic Spurs SSB Phase Noise at MHz SSB Phase Noise at MHz SSB Phase Noise at 125MHz SSB Phase Noise at 1MHz RJ 25MHz crystal input (Note 9) 25MHz or differential input (Notes 9, 1) 12kHz to 2MHz MHz to 2MHz ps RMS (Note 11) -74 dbc (Note 11) -49 dbc or LVDS (Note 11) 1 ps P-P (Note 12) -7 dbc f OFFSET = 1kHz -111 f OFFSET = 1kHz -113 f OFFSET = 1kHz -119 f OFFSET = 1MHz -136 f OFFSET R 1MHz -147 f OFFSET = 1kHz -117 f OFFSET = 1kHz -119 f OFFSET = 1kHz -125 f OFFSET = 1MHz -142 f OFFSET R 1MHz -151 f OFFSET = 1kHz -124 f OFFSET = 1kHz -125 f OFFSET = 1kHz -131 f OFFSET = 1MHz -147 f OFFSET R 1MHz -153 f OFFSET = 1kHz -126 f OFFSET = 1kHz -127 f OFFSET = 1kHz -133 f OFFSET = 1MHz -148 f OFFSET R 1MHz -152 dbc/ Hz dbc/ Hz dbc/ Hz dbc/ Hz 4

5 ELECTRICAL CHARACTERISTICS (continued) (V CC = +3.V to +3.6V, T A = -4 C to +85 C. Typical values are at V CC =, T A = +25 C, unless otherwise noted. Signal applied to CIN or / only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SSB Phase Noise at 66.67MHz f OFFSET = 1kHz -13 f OFFSET = 1kHz -131 f OFFSET = 1kHz -137 f OFFSET = 1MHz -152 f OFFSET R 1MHz -156 Note 1: A series resistor of up to 1.5I is allowed between V CC and V CCA for filtering supply noise when system power-supply tolerance is V CC = 3.3V Q5%. See Figure 3. Note 2: Measured with all outputs enabled and unloaded. Note 3: CIN can be AC- or DC-coupled. See Figure 8. Input high voltage must be V CC +.3V. Note 4: can be AC- or DC-coupled. See Figure 1. Note 5: Measured with 1I differential load. Note 6: Measured with crystal input, or with 5% duty cycle or differential input. Note 7: Measured with output termination of 5I to V CC - 2V or Thevenin equivalent. Note 8: Measured with a series resistor of 33I to a load capacitance of 3.pF. See Figure 1. Note 9: Measured at 125MHz output. Note 1: Measured using /LVTTL input with slew rate R 1.V/ns, or differential input with slew rate R.5V/ns. Note 11: Measured at 125MHz output with 2kHz, 5mV P-P sinusoidal signal on the supply using the crystal input and the power-supply filter shown in Figure 3. See the Typical Operating Characteristics for other supply noise frequencies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to Application Note 4461: HFAN-4.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers. Note 12: Measured with all outputs enabled and all three banks at different frequencies. dbc/ Hz QCC 33Ω 499Ω OSCILLOSCOPE 3pF 5Ω Figure 1. Output Measurement Setup 5

6 (V CC = 3.3V, T A = +25, unless otherwise noted.) SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE ( OUTPUTS, ALL ENABLED) PLL NORMAL, ALL OUTPUTS LOADED PLL BYPASS, ALL OUTPUTS LOADED PLL NORMAL, ALL OUTPUTS UNLOADED 5 PLL BYPASS, ALL OUTPUTS UNLOADED TEMPERATURE ( C) toc1 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE (LVDS OUTPUTS, ALL ENABLED) PLL NORMAL PLL BYPASS TEMPERATURE ( C) Typical Operating Characteristics toc2 SUPPLY CURRENT (ma) SUPPLY CURRENT vs. TEMPERATURE ( OUTPUTS, ALL LOADED) QA[4:3], QA[2:], QB[2:], QC, AND QCC ENABLED QA[4:3], QA[2:], AND QB[2:] ENABLED QA[4:3] AND QA[2:] ENABLED QA[2:] ENABLED ALL OUTPUTS DISABLED TEMPERATURE ( C) toc SUPPLY CURRENT vs. TEMPERATURE (LVDS OUTPUTS) QA[4:3], QA[2:], QB[2:], QC, AND QCC ENABLED toc4 DIFFERENTIAL OUTPUT AT 5MHz () toc5 DIFFERENTIAL OUTPUT AT MHz () toc6 SUPPLY CURRENT (ma) QA[4:3], QA[2:], AND QB[2:] ENABLED QA[4:3] AND QA[2:] ENABLED QA[2:] ENABLED ALL OUTPUTS DISABLED 2mV/div 2mV/div TEMPERATURE ( C) 3ps/div 6ps/div DIFFERENTIAL OUTPUT AT 125MHz () toc7 DIFFERENTIAL OUTPUT AT 125MHz (LVDS) toc8 QCC OUTPUT AT 66.67MHz () toc9 2mV/div 1mV/div 5mV/div 1.2ns/div 1.2ns/div 2ns/div 6

7 Typical Operating Characteristics (continued) (V CC = 3.3V, T A = +25, unless otherwise noted.) OUTPUT SWING (mvp-p) OUTPUT SWING vs. OUTPUT FREQUEY LVDS OUTPUT FREQUEY (MHz) toc1 OUTPUT SWING (mvp-p) OUTPUT SWING vs. TEMPERATURE LVDS TEMPERATURE ( C) toc11 RISE/FALL TIME (ps) RISE/FALL TIME vs. TEMPERATURE (2% TO 8%) LVDS TEMPERATURE ( C) toc12 DUTY-CYCLE DISTORTION (%) DUTY-CYCLE DISTORTION vs. TEMPERATURE /LVDS toc13 PHASE NOISE (dbc/hz) PHASE NOISE AT MHz PHASE JITTER =.28ps RMS INTEGRATED 12kHz TO 2MHz toc14 PHASE NOISE (dbc/hz) PHASE NOISE AT MHz PHASE JITTER =.28ps RMS INTEGRATED 12kHz TO 2MHz toc TEMPERATURE ( C) -16 1k 1k 1k 1M OUTPUT FREQUEY (Hz) 1M 1M -16 1k 1k 1k 1M OUTPUT FREQUEY (Hz) 1M 1M PHASE NOISE AT 125MHz PHASE JITTER =.33ps RMS INTEGRATED 12kHz TO 2MHz toc PHASE NOISE AT 1MHz PHASE JITTER =.36ps RMS INTEGRATED 12kHz TO 2MHz toc PHASE NOISE AT 66.67MHz PHASE JITTER =.38ps RMS INTEGRATED 12kHz TO 2MHz toc18 PHASE NOISE (dbc/hz) PHASE NOISE (dbc/hz) PHASE NOISE (dbc/hz) k 1k 1k 1M OUTPUT FREQUEY (Hz) 1M 1M -16 1k 1k 1k 1M OUTPUT FREQUEY (Hz) 1M 1M -16 1k 1k 1k 1M OUTPUT FREQUEY (Hz) 1M 1M 7

8 Typical Operating Characteristics (continued) (V CC = 3.3V, T A = +25, unless otherwise noted.) INTEGRATED PHASE JITTER (psrms) INTEGRATED PHASE JITTER (12kHz TO 2MHz) vs. TEMPERATURE.6 OUTPUT FREQUEY = 125MHz TEMPERATURE ( C) LVDS toc19 JITTER TRANSFER (db) k 1k JITTER TRANSFER 1k JITTER FREQUEY (Hz) 1M toc2 1M SPUR AMPLITUDE (dbc) SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUEY f C = 125MHz, NOISE = 5mV P-P LVDS NOISE FREQUEY (khz) toc21 DETERMINISTIC JITTER (psp-p) DETERMINISTIC JITTER INDUCED BY POWER- SUPPLY NOISE vs. NOISE FREQUEY 4 f C = 125MHz, NOISE = 5mV P-P /LVDS NOISE FREQUEY (khz) toc22 8

9 PIN NAME FUTION 1 DM /LVTTL Input. Three-level control for input divider M. See Table 3. 2 XIN Crystal Oscillator Input 3 XOUT Crystal Oscillator Output 4 V CC Core Power Supply. Connect to. 5 IN_SEL /LVTTL Input. Three-level control for input mux. See Table 1. 6 PLL_BP /LVTTL Input. Three-level control for PLL bypass mode. See Table 2. 7, 8 DF1, DF /LVTTL Inputs. Three-level controls for feedback divider F. See Table 4. Pin Description 9 QC_CTRL /LVTTL Input. Three-level control input for C-bank output interface. See Table 1. 1 V CCA Power Supply for Internal Voltage-Controlled Oscillators (VCOs). See Figure RES Reserved. Connect to GND for normal operation. 12 DP /LVTTL Input. Three-level control for prescale divider P. See Table 7. 13, 14 DB1, DB /LVTTL Inputs. Three-level controls for output divider B. See Table 5. 15, 16 DA1, DA /LVTTL Inputs. Three-level controls for output divider A. See Table 5. 17, 18 DC1, DC /LVTTL Inputs. Three-level controls for output divider C. See Table QA_CTRL2 /LVTTL Input. Three-level control for QA[4:3] output interface. See Table 8. 2 V CCQCC Power Supply for QCC Output. Connect to. 21 QCC C-Bank Clock Output 22, 23 QC, QC C-Bank Differential Output. Configured as or LVDS with the QC_CTRL pin. 24 V CCQC Power Supply for C-Bank Differential Output. Connect to. 25, 36 V CCQA Power Supply for A-Bank Differential Outputs. Connect to. 26, 27 QA4, QA4 A-Bank Differential Output. Configured as or LVDS with the QA_CTRL2 pin. 28, 29 QA3, QA3 A-Bank Differential Output. Configured as or LVDS with the QA_CTRL2 pin. 3, 31 QA2, QA2 A-Bank Differential Output. Configured as or LVDS with the QA_CTRL1 pin. 32, 33 QA1, QA1 A-Bank Differential Output. Configured as or LVDS with the QA_CTRL1 pin. 34, 35 QA, QA A-Bank Differential Output. Configured as or LVDS with the QA_CTRL1 pin. 37 V CCQB Power Supply for B-Bank Differential Outputs. Connect to. 38, 39 QB, QB B-Bank Differential Output. Configured as or LVDS with the QB_CTRL pin. 4, 41 QB1, QB1 B-Bank Differential Output. Configured as or LVDS with the QB_CTRL pin. 42, 43 QB2, QB2 B-Bank Differential Output. Configured as or LVDS with the QB_CTRL pin. 44 QA_CTRL1 /LVTTL Input. Three-level control for QA[2:] output interface. See Table QB_CTRL /LVTTL Input. Three-level control for B-bank output interface. See Table 9. 46, 47, Differential Clock Input. Operates up to 35MHz. This input can accept DC-coupled signals, and is internally biased to accept AC-coupled LVDS, CML, and signals. 48 CIN Clock Input. Operates up to 16MHz. EP Exposed Pad. Connect to supply ground for proper electrical and thermal performance. 9

10 Detailed Description The is a low-jitter clock generator designed to operate over a wide range of frequencies. It consists of a selectable reference clock (on-chip crystal oscillator, input, or differential input), PLL with on-chip VCO, pin-programmable dividers and muxes, and three IN_SEL DM V CC V CCA banks of clock outputs. See Figure 2. The output banks include nine pin-programmable LVDS/ output buffers and one output buffer. The frequency, enabling, and output interface of each output bank can be individually programmed. In addition the A-bank is split into two banks with programmable enabling and DP DA[1:] 2 PLL_BP V CCQA QA_CTRL1 QA XOUT CRYSTAL OSCILLATOR 1 QA QA1 QA1 XIN CIN M PFD f REF f PFD 15MHz TO 42MHz f VCO CP VCO P A 383MHz TO 425MHz fqa / QA2 QA2 QA3 QA3 1 F QA4 QA4 QA_CTRL2 V CCQB QB_CTRL QB QB QB1 1 QB1 B f QB / QB2 QB2 DIVIDER A: 2, 3, 4, 5, 6, 8, 1, 12, 15 DIVIDER B: 2, 3, 4, 5, 6, 8, 1, 12, 15 DIVIDER C: 3, 5, 6, 8, 1, 12, 15, 2, 3 DIVIDER F: 16, 2, 24, 25, 28, 3, 32, 4, 48 DIVIDER M: 1, 2, 4 DIVIDER P: 4, 5, 6 1/ QC_CTRL QC QC C f QC QCC EP DF[1:] DB[1:] DC[1:] V CCQC V CCQCC Figure 2. Detailed Functional Diagram 1

11 output interface. A PLL bypass mode is also available for system testing or clock distribution. Crystal Oscillator The on-chip crystal oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between XIN and XOUT. See the Crystal Selection and Layout section for more information. The XIN and XOUT pins can be left open if not used. Clock Input An -compatible clock source can be connected to CIN to serve as the PLL reference clock. The input is internally biased to allow AC- or DC-coupling (see the Applications Information section). It is designed to operate from 15MHz to 16MHz. No signal should be applied to CIN if not used. Differential Clock Input A differential clock source can be connected to to serve as the PLL reference clock. This input operates from 15MHz to 35MHz and contains an internal 1ω differential termination. This input can accept DC-coupled signals, and is internally biased to accept AC-coupled LVDS, CML, and signals (see the Applications Information section). No signal should be applied to if not used. Phase-Locked Loop (PLL) The PLL takes the signal from the crystal oscillator, clock input, or differential clock input and synthesizes a low-jitter, high-frequency clock. The PLL contains a phase-frequency detector (PFD), a charge pump (CP), and a low phase noise VCO with a wide 3.83GHz to 4.25GHz frequency range. The high-frequency VCO output is divided by prescale divider P and then is connected to the PFD input through a feedback divider. The PFD compares the reference frequency to the divided-down VCO output and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO/P output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies. Dividers and Muxes The dividers and muxes are set with three-level control inputs. Divider settings and routing information are given in Tables 1 to 7. See Table 11 for example divider configurations used in various applications. Table 1. PLL Input IN_SEL INPUT Crystal Input. XO circuit is disabled when not selected. 1 Differential Input. No signal should be applied to if not selected. Input. No signal should be applied to CIN if not selected. Table 2. PLL Bypass PLL_BP PLL OPERATION PLL Enabled for Normal Operation. All outputs from the A, B, and C banks are derived from the VCO. 1 PLL Bypassed. Selected input passes directly to the outputs. The VCO is disabled to minimize power consumption and intermodulation spurs. Used for system testing or clock distribution. The outputs from A-bank and B-bank are derived from the VCO, but the C-bank outputs are directly driven from the input signal for purposes of daisy chaining. 11

12 Table 3. Input Divider M DM Table 5. Output Divider A, B Table 6. Output Divider C M DIVIDER RATIO Note: When the on-chip XO is selected (IN_SEL = ), the setting DM = is required. Table 4. PLL Feedback Divider F DF1 DF F DIVIDER RATIO DA1/DB1 DA/DB A, B DIVIDER RATIO DC1 DC C DIVIDER RATIO Table 7. Prescale Divider P Table 8. A-Bank Output Interface QA_CTRL1 Table 9. B-Bank Output Interface Table 1. C-Bank Output Interface QC_CTRL QC AND QCC OUTPUT QC = LVDS, QCC = 1 QC =, QCC = DP P DIVIDER RATIO QA[2:] OUTPUT QA[2:] = LVDS 1 QA[2:] = QA_CTRL2 QA[2:] disabled to high impedance QA[4:3] OUTPUT QA[4:3] = LVDS 1 QA[4:3] = QB_CTRL QA[4:3] disabled to high impedance QB[2:] OUTPUT QB[2:] = LVDS 1 QB[2:] = QB[2:] disabled to high impedance QC and QCC disabled to high impedance LVDS/ Clock Outputs The differential clock outputs (QA[4:], QB[2:], QC) operate up to 8MHz and have a pin-programmable LVDS/ output interface. See Tables 8 to 1. When configured as LVDS, the buffers are designed to drive transmission lines with a 1ω differential termination. When configured as, the buffers are designed to drive transmission lines terminated with 5ω to VCC - 2V. Unused output banks can be disabled to high impedance and unused outputs can be left open. Clock Output The clock output operates up to 16MHz and is designed to drive a single-ended high-impedance load. If unused, this output can be left open or the C-bank can be disabled to high impedance. 12

13 Internal Reset During power-on, a power-on reset (POR) signal is generated to synchronize all dividers. A reset signal is also generated if any control pin is changed. Outputs within a bank are phase aligned, but outputs bank-to-bank may not be phase aligned. Applications Information Output Frequency Configuration The output frequencies (fqa, fqb, fqc) are functions of the reference frequency (fref) and the pinprogrammable dividers (A, B, C, F, M). The relationships can be expressed as: fref F fqa = M A (1) fref F fqb = M B (2) fref F fqc = M C (3) The frequency ranges for the selected reference clocks are 18MHz to 33.5MHz for the crystal oscillator input, 15MHz to 16MHz for the input, and 15MHz to 35MHz for the differential input. The available dividers are given in Tables 3 to 6. For a given reference frequency fref, the input divider M, the PLL feedback divider F, and VCO prescale divider P must be configured so the VCO frequency (fvco) falls within the specified ranges. Invalid PLL configuration leads to VCO frequencies beyond the specified ranges and can result in loss of lock. An expression for the VCO frequency along with the specified ranges is given by: f f REF VCO = F P (4) M 383MHz fvco 425MHz (5) The prescale divider P is set by DP as given in Table 7. In addition, the reference clock frequency and input divider M must also be selected so the PFD compare frequency (fpfd) falls within the specified range of 15MHz to 42MHz. If applicable, the higher fpfd should be selected for optimal jitter performance. fref f f VCO PFD = = M P F (6) 15MHz fpfd 42MHz (7) Note that the reference clock frequency is not limited by the fpfd range when the PLL is in bypass mode. Example Frequency Configuration The following is an example of how to find divider ratios for a valid PLL configuration, given a requirement of input and output frequencies. 1) Select input and output frequencies for system clocking. fref = 25MHz fqa = 125MHz fqb = 1MHz fqc = 66.67MHz 2) Find the input divider M for a valid PFD compare frequency. Using Table 3 and equations (6) and (7), it is determined that M = 1 is the only valid option. 3) Find the feedback divider F and prescale divider P for a valid fvco. Using Tables 4 and 7 along with equations (4) and (5), it is determined that F = 4 and P = 4 results in fvco = 4MHz, which is within the valid range of the VCO. 4) Find the output dividers A, B, C for the required output frequencies. Using Tables 5 and 6 and equations (1), (2), and (3), it is determined that A = 8 gives fqa = 125MHz, B = 1 gives fqb = 1MHz, and C = 15 gives fqc = 66.67MHz. Table 11 provides input and output frequencies along with valid divider ratios for a variety of applications. 13

14 Table 11. Reference Frequencies and Divider Ratios for Various Applications f REF (MHz) INPUT DIVIDER (M) PLL FEEDBACK DIVIDER (F) VCO FREQUEY (MHz) VCO PRESCALE DIVIDER (P) OUTPUT DIVIDER (A, B, C) OUTPUT FREQUEY (MHz) APPLICATIONS Wireless Base Station: WCDMA, cdma2, LTE, TD_SCDMA 33.3/66.7/ /2/ /5/1 1/2/ /66.7/ /2/ /5/1 1/2/ / 62.5/125 1/2/ Server, Network Processor, DDR/ QDR Memory, PCIe, SATA Server, FB-DIMM, Network Processor, DDR/ QDR Memory, PCIe, SATA Microwave Radio Link OTU1, 1Gbps SONET with FEC Gbps Ethernet with FEC Gbps FC OTU2, 1Gbps SONET with Digital Wrapper cdma2 is a registered trademark of the Telecommunications Industry Association. 14

15 Power-Supply Filtering The is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. To take full advantage of on-board filtering and noise attenuation, in addition to excellent on-chip power-supply rejection, this part provides a separate power-supply pin, VCCA, for the VCO circuitry. Figure 3 illustrates the recommended power-supply filter network for VCCA. The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is ±5%. Decoupling capacitors should be used on all other supply pins for best performance. All supply connections should be driven from the same source. V CC V CCA Figure 3. Power-Supply Filter 1.5Ω ±5% 1µF Ground Connection The 48-pin TQFN package features an exposed pad (EP), which provides a low resistance thermal path for heat removal from the IC and also the electrical ground. For proper operation, the EP must be connected to the circuit board ground plane with multiple vias. Crystal Selection and Layout The features an integrated on-chip crystal oscillator to minimize system implementation cost. The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 12 for recommended crystal specifications. See Figure 4 for the crystal equivalent circuit and Figure 5 for the recommended external capacitor connections. The crystal, trace, and two external capacitors should be placed on the board as close as possible to the XIN and XOUT pins to reduce crosstalk of active signals into the oscillator. The total load capacitance for the crystal is a combination of external and on-chip capacitance. The layout shown in Figure 6 gives approximately 1.7pF of trace plus footprint capacitance per side of the crystal. Note the ground plane is removed under the crystal to minimize capacitance. There is approximately 2.5pF of on-chip capacitance between XIN and XOUT. With an external 27pF capacitor connected to XIN and a 33pF external capacitor connected to XOUT, the total load capacitance for the crystal is approximately 18pF. The XIN and XOUT pins can be left open if not used. Table 12. Crystal Selection Parameters PARAMETER SYMBOL MIN TYP MAX UNITS Crystal Oscillation Frequency f OSC MHz Shunt Capacitance C pf Load Capacitance C L 18 pf Equivalent Series Resistance (ESR) R S 1 5 I Maximum Crystal Drive Level 2 FW XTAL 27pF XIN C CRYSTAL (C L = 18pF) RS L S C S 33pF XOUT Figure 4. Crystal Equivalent Circuit Figure 5. Crystal, Capacitor Connections 15

16 Figure 6. Crystal Layout V CC 1.4V V BIAS Interfacing with Input The equivalent input circuit for CIN is given in Figure 7. This input is internally biased to allow AC- or DC-coupling, and has 18kI input impedance. See Figure 8 for the interface circuit. No signal should be applied to CIN if not used. Interfacing with Differential Input The equivalent input circuit for is given in Figure 9. This input operates up to 35MHz and contains an internal 1I differential termination as well as a 35I common-mode termination. The common-mode termination ensures good signal integrity when connected to a source with large common-mode signals. The input can accept DC-coupled signals, and is internally biased to accept AC-coupled LVDS, CML, and signals (Figure 1). No signal should be applied to if not used. 18kΩ V CC CIN V CC ESD STRUCTURES ESD STRUCTURES Figure 7. Equivalent CIN Circuit 5Ω 2kΩ DC-COUPLED V CC 5Ω 1Ω 16pF V CC - 1.3V 2kΩ XO CIN ESD STRUCTURES Figure 9. Equivalent Circuit AC-COUPLED XO CIN Figure 8. Interface to CIN 16

17 SOURCE DRIVING DIFFERENTIAL INPUT DC-COUPLED 15Ω 1Ω Interfacing with Outputs The equivalent output circuit is given in Figure 11. These outputs are designed to drive a pair of 5ω transmission lines terminated with 5ω to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other terminations methods can be used, as shown in Figure 12. For more information on terminations and how to interface with other logic families, refer to Application Note 291: HFAN-1.: Introduction to LVDS, PECL, and CML. 15Ω V CC SOURCE DRIVING DIFFERENTIAL INPUT AC-COUPLED 15Ω 1Ω 15Ω ESD STRUCTURES LVDS OR CML SOURCE DRIVING DIFFERENTIAL INPUT AC-COUPLED V DD Figure 11. Equivalent Output Circuit LVDS OR CML 1Ω Figure 1. Interfacing to 17

18 DC-COUPLED DRIVING THEVENIN EQUIVALENT TERMINATION 13Ω 13Ω HIGH IMPEDAE WITH/WITHOUT DC BIAS 82Ω 82Ω AC-COUPLED DRIVING INTERNAL 1Ω DIFFERENTIAL TERMINATION V DD 15Ω 1Ω ON-CHIP TERMINATION WITH DC BIAS 15Ω AC-COUPLED DRIVING EXTERNAL 5Ω WITH COMMON-MODE TERMINATION V DD 15Ω HIGH IMPEDAE WITH DC BIAS 15Ω 5Ω 5Ω Figure 12. Interface to Outputs 18

19 V REG V CC 5Ω Interfacing with LVDS Outputs The equivalent LVDS output circuit is given in Figure 13. These outputs provide 1ω differential output impedance designed to drive a 1ω differential transmission line terminated with a 1ω differential load. Example interface circuits are shown in Figure 14. For more information on LVDS terminations and how to interface with other logic families, refer to Application Note 291: HFAN- 1.: Introduction to LVDS, PECL, and CML. 5Ω ESD STRUCTURES Interfacing with Output The equivalent output circuit is given in Figure 15. This output provides 15ω output impedance and is designed to drive a high-impedance load. A series resistor of 33ω is recommended at the output before the transmission line. An example interface circuit is shown in Figure 16. Figure 13. Equivalent LVDS Output Circuit V CCQCC DC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT 1Ω QCC LVDS LVDS* 1Ω ESD STRUCTURES AC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT Figure 15. Equivalent Output Circuit V DD LVDS LVDS* QCC 33Ω HIGH IMPEDAE *1Ω DIFFERENTIAL INPUT IMPEDAE ASSUMED. Figure 16. Interface to Output Figure 14. Interface to LVDS Outputs 19

20 Layout Considerations The inputs and outputs are the most critical paths for the ; great care should be taken to minimize discontinuities on the transmission lines. Here are some suggestions for maximizing the performance of the : An uninterrupted ground plane should be positioned beneath the clock outputs. The ground plane under the crystal should be removed to minimize capacitance. Supply decoupling capacitors should be placed close to the supply pins, preferably on the same side of the board as the. Take care to isolate input traces from the outputs. The crystal, trace, and two external capacitors should be placed on the board as close as possible to the XIN and XOUT pins to reduce crosstalk of active signals into the oscillator. Maintain 1ω differential (or 5ω single-ended) transmission line impedance into and out of the part. Provide space between differential output pairs to reduce crosstalk, especially if the outputs are operating at different frequencies. Use multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the evaluation kit for more information. PROCESS: BiCMOS Chip Information Pin Configuration TOP VIEW VCCQA QA QA QA1 QA1 QA2 QA2 QA V CCQB V CCQC QB QC QB QC QB QCC QB V CCQCC QB QA_CTRL2 QB DC QA_CTRL DC1 QB_CTRL DA *EP DA1 DB CIN DB DM XIN XOUT VCC IN_SEL PLL_BP DF1 DF QC_CTRL VCCA RES DP QA3 QA4 QA4 VCCQA THIN QFN (7mm 7mm.8mm) *THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. 2

21 27pF XIN 1.5Ω 1µF V CCA V CC V CCQA V CCQB V CCQC V CCQCC QA[4:] Typical Application Circuits 15Ω 125MHz ASIC WITH TERMINATION 25MHz 33pF XOUT CIN QA[4:] 15Ω 1Ω IN_SEL PLL_BP QB[2:] 1MHz LVDS ASIC WITH LVDS TERMINATION 1Ω DM DF1 QB[2:] DF DA1 DA QC 66.67MHz LVDS ASIC WITH LVDS TERMINATION DB1 DB 1Ω DC1 QC DC DP RES QA_CTRL1 QCC 33Ω 66.67MHz ASIC WITH TERMINATION QA_CTRL2 QB_CTRL HIGH IMPEDAE QC_CTRL EP 21

22 CLOCK GENERATOR FOR ETHERNET AND SYSTEM CLOCKING 25MHz XIN XOUT Typical Application Circuits (continued) QA[4:] QB[2:] 312.5MHz OR LVDS MHz OR LVDS BACKPLANE TRANSCEIVER 1GbE PHY MAX3637 QCC 25MHz ASIC QC 25MHz QA[4:] 125MHz OR LVDS 1GbE PHY QB[2:] 1MHz OR LVDS PCIe QC 66.67MHz OR LVDS NETWORK PROCESSOR QCC 66.67MHz FPGA FREQUEY TRANSLATOR FOR BASE STATION 3.72MHz QA[4:] QB[2:] MHz OR LVDS MHz OR LVDS ASIC CPRI SerDes QC 3.72MHz OR LVDS FPGA QCC 3.72MHz FPGA Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFN-EP T Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 Maxim Integrated Products, 12 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.