Cl. Cl. ..., V, V, -I..., - QJ d.

Transcription

1 )> Cl. Cl...., m V, V, -I..., QJ :J V, - QJ d. 0 :J

2 Main Points Address Translation Concept - How do we convert a virtual address to a physical address? Flexible Address Translation I R. lz G.z: f1..t:?z:.mo/2_'-( ON.s OF V,I a.. TU AL - Segmentation --k_ LvMPL lz?< MF=f1 MGT - Paging _r= L}: NS Afl.. C ()\JJ- (la6 Sz. D ~ /J, DD f?_i;.ss (_ - i3ad {? 0 /l.. sfaflsr'z A()O/l~SS u~ag~ - Multilevel translation ~,f ~c~ Efficient Address Translation IS o,h - C & p '-( o/\j W/L 2 i ~ - Translation Lookaside Buffers 5 Z-AC:: I( G (l_o~t ~l - Virtually and physically addressed caches l. DA O ON i) G. MANO

3 Address Translation Concept Mrtu Virtual Address Processor l >I Translation I Invalid Raise. Exception ~ Valid Data "" ~ > Physical Address Physical Memory... Data

4 (_'[tj fz.arl p AC:. r-z Tl\ r'1 L fz S Beyond Paging: Sparse Address Spaces Might want many separate segments - Per-processor heaps - Per-thread stacks - Memory-mapped files - Dynamically linked libraries What if virtual address space is large? - 32-bits, 4KB pages=> SOOK page table entries - 64-bits => 4 quadrillion page table entries

5 Multi-level Translation Tree of translation tables - Paged segmentation - Multi-level page tables - Multi-level paged segmentation All have pages as lowest level; why?

6 Multilevel Translation with Pages at Lowest Level Efficient memory allocation (vs. segments) Efficient for sparse addresses (vs. 1 level paging) Efficient disk transfers (fixed size units) Easier to build translation lookaside buffers Efficient reverse lookup (from physical -> virtual) Variable granularity for protection/sharing Cc.)/t Si_ 11Af Except: see discussion of superpages

7 Paged Segmentation Process memory is segmented Segment table entry: - Pointer to page table - Page table length {# of pages in segment) - Access permissions Page table entry: - Page frame - Access permissions (~,,~t )(~ 6 -:1 '2... l:,,-._ x 8'b < r'-:-"-+1 ~ -z_ ( ~c,.,c. ( PT) Share memory or set access permissions at either page or segment-level

8 v: r+,_( -f,()o{l ('11-.., I"'""-'-( t_. 5-f-i_c({ 1<~ ~' ~~~ -r~ ;,-,_ Processor )' ~( ~ ~'"3l. ~jl- ~~ -Z.- Si-s.-v.t- fe.,.. /"3 Implementation ; f--i Li-; ~ t..s Ct>~ (' t-,,..- --~\ Virtual, 1 Address J C ~ _., \ )..-p_.r It) c.f~r ~\ -- : \ / I I : ~ Segment/ Page Offset... - ( -:. L ~ > Exception... Segme~t Table Page Table c~... ~ r::.. ':':I.... ~.s"~ Page Table Frame Access \ Read ' Size Access Read Physical... >... Read Address R/W R/W R/W... ""... ->I Frame I Offset > Physical Memory

9 Question With paged segmentation, what must be saved/restored across a process context switch? \

10 Multi-level or hierarchical page tables ~7 ~lv,x~b Ex: 2-level page table - Level 1 table: each PTE points to a page table - Level 2 table: each PTE. points to a page Can share/protect/page in/out at either level 1 or level 2 L4-"~( \ t~_,t.( 't. ½ (( ~ Level 1 Table. Level2 Tables?_H/3 I { 0 (0 O~'S ~+ ~-z_ ~,1 \ (.. ~' ~~

11 Implementation Physical Memory Processor Virtual Address >I Index 1 I Index 2 I Index 3 I Offset ] : Physical j Level 1 Address l Iii : ~ t Frame I Offset ]... ~ I I... Level 2 :. > : > Level > t

12 x86 Multilevel Paging, Omit sub-tree if no valid addresses - Good for sparse address space 4KB pages Each level of page table fits in one page 32-bit: two level page table (per segment) 64-bit: four level page table (per segment)

13 x86-32 Paging I VPN3 I VPN4 I VPO I -- -, _ - "',---", l i Virtual address Page Directory Page Table i ' ~ PDE ~ ~ PTE = CR3 -,c=..... i.. 20 l 12 ' I PPN I PPO I cal address,.. - -

14 x86-64 Paging 16 9 l VPN1 --= - " i l ,-;.. - -,..;c, VPN2 I VPN3 I VPN4 I. - -,i' " , ,-.,;-:-':...,,_ - -.., ; Page 12 VPO Virtual address --- " ;...C,.,,,.;.. -I Page Map Level4 Directory Pointer Table Page Directory Page Table l ' L\ '?5 b rt S o \ v-:, tu.j A O 0) R.~ ~<; CR3 ~ PM4LE.;... PDPE..... PDE.,... PTE. -- ' ~ - -~ -- L...i s. I I:. TC3 s~...rv~ 8 I 36 i 12 PPN l PPO I cal address ~l < b ~ 0 <?- ~k, ~~~J 4\-O0aJiSS 7-S t 1 (s

15 Page table entries (x86 32 bit) f"'\o O L ri ~ Ji O 0 -: f?_ty A cce_ s<; ( tj.s ~ S \1-J Empty Ignored 0 4KB page Bits 31:12 of address of page frame lgn l GI O Pl Pl UR / /I 1 f '-Y? '\-r~---- 'l. t:i. l\~" ~re\ I ;Ave.(~& ~,e. ( S/o') Cc_ Cl, C. W i-+ ~ {_ I/0 ) "'r ~ ( s"7" s +~,...+ (LAM -ft.eo vs f \1/ us~ r / 5 u f<?...rv:sor \!') \ <!..... ll -w r,-{ ' d\ t"'e. ~~ - 01\. \y

16 Page directory e. 5 (x86 32 bit) \/fl '-1, us~ Q:.:rT G, Empty Ignored 0 4MB page Bits 31:22 of address of 4MB page frame 0 lgn Pl Pl UR / /I 1 Page table Bits 31:12 of address of page table cac\--\~~ 0 '1:,S A- ~LVZ- c_-r:.,/ o) lgn I ol g n ~)R c ~= (---/ ~,)\,'{ w r~t e.. *(bu,~ [--s/o'> ~ e (t,,#., O r,1 v-z ~ ', ;,;_'r~ '7),, ~y \)',e.,( o 90~ Dr) (,v v

17 Small page translation CR3 register Address of page directory SBZ Virtual address PDE index PTEindex Offset Address of PDE Address of page directory PDE Page table base address Note: addresses in physical memory! Address of PTE Page table base address PTE Small page base address Access control 11 Physical address Small page base address Offset

18 Page table for small pages Base address 1024 entries 4kB 4kB page 1024 entries 4kB Translates VA[21:12] Page table 4kB page Page director VA[ll:O] = offset in page Translates VA[31:22] Page table

19 Question Write pseudo-code for translating a virtual address to a physical address for a system using 3-level paging, with 8 bits of address per level p TI) r ADt>«. '>'> ;lli J I p ( LA l)pe_ '> ">,~ g_ Ox~]

20 x86 Multilevel Paged Segmentation Global Descriptor Table (segment table) Each segment descriptor - Pointer to (multilevel) page table - Segment length - Segment access permissions Context switch - change global descriptor table register (GDTR), pointer to global descriptor table - Side effect: invalidates TLB

21 Multilevel Translation Pros: - Allocate/fill only page table entries that are in use - Simple memory allocation - Share at segment or page level Cons: - Space overhead: one pointer per virtual page - Multip le lookups per memory reference

22 Page Translation in the OS OS's need to keep their own data structures - List of memory objects (segments) - Virtual page-> physical page frame - Physical page frame-> set of virtual pages - Keep track of copy on write, load on demand,... Why not just use the hardware page tables?

23 Kernel Page Translation Kernel maintains its own page translation data structures - Portable, flexible - Copy changes down into hardware page tables Example: Inverted page table - Hash from virtual page-> physical page - Space proportional to# of physical pages Example: virtual/shadow page table - Linux kernel tables mirror x86 structure, even on ARM