IDT71V124SA/HSA. 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout

Transcription

1 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout IDT71VSA/HSA Features K x advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/gnd) for reduced noise Equal access and cycle times Commercial: ///2 Industrial: ///2 One Chip Select plus one Output Enable pin Inputs and outputs are LVTTL-compatible Single 33V supply Low power coumption via chip deselect Available in a 32-pin 3- and -mil Plastic SOJ, and 32-pin Type II TSOP packages Description The IDT71V is a 1,,576-bit high-speed static RAM organized as K x It is fabricated using IDT s high-performance, high-reliability CMOS technology This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs The JEDEC center power/gnd pinout reduces noise generation and improves system performance The IDT71V has an output enable pin which operates as fast as 5, with address access times as fast as 9 available All bidirectional inputs and outputs of the IDT71V are LVTTL-compatible and operation is from a single 33V supply Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation Functional Block Diagram A A16 DECODER 1,,576-BIT MEMORY ARRAY I/O -I/O7 I/O CONTROL WE OE CONTROL LOGIC 373 drw Integrated Device Technology, Inc 1 OCTOBER 2 DSC-373/9

2 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Pin Configuration Truth Table (1) Capacitance A A1 A2 A I/O 6 SO I/O1 7 SO VDD GND I/O2 I/O3 WE 9 11 SO A 13 2 A A6 1 A SOJ and TSOP Top View A16 A A1 A13 OE I/O7 I/O6 GND VDD I/O5 I/O A A11 A A9 A 373 drw 2 OE WE I/O Function L L H DATAOUT Read Data L X L DATAIN Write Data L H H High-Z Output Disabled H X X High-Z Deselected Standby NOTE: 1 H = VIH, L = VIL, X = Don't care 373 tbl 1 (TA = +25 C, f = MHz, SOJ package) Symbol Parameter (1) Conditio Max Unit CIN Input Capacitance VIN = 3dV 6 pf CI/O I/O Capacitance VOUT = 3dV 7 pf 373 tbl 3 NOTE: 1 This parameter is guaranteed by device characterization, but is not production tested Absolute Maximum Ratings (1) Recommended DC Operating Conditio DC Electrical Characteristics (VDD = Min to Max, Commercial and Industrial Temperature Ranges) Symbol Rating Value Unit VDD VIN, VOUT TA Supply Voltage Relative to GND Terminal Voltage Relative to GND Commercial Operating Temperature Industrial Operating Temperature -5 to +6 V -5 to VDD+5 V - to +7 - to +5 TBIAS Temperature Under Bias -55 to +5 o C TSTG Storage Temperature -55 to +5 o C PT Power Dissipation 5 W IOUT DC Output Current 5 ma NOTE: 373 tbl 2 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied Exposure to absolute maximum rating conditio for extended periods may affect reliabilty Symbol Parameter Min Typ Max Unit VDD (1) Supply Voltage V VDD (2) Supply Voltage V VSS Ground V VIH Input High Voltage 2 VDD+3 (3) V VIL Input Low Voltage 5 (1) V 1 For 71VSA only 2 For all speed grades except 71VSA 3 VIH (max) = VDD+2V for pulse width less than 5, once per cycle VIL (min) = 2V for pulse width less than 5, once per cycle Symbol Parameter Test Conditio Min Max Unit ILI Input Leakage Current VDD = Max, VIN = GND to VDD Recommended Operating Temperature and Supply Voltage Grade Temperature GND VDD Commercial C to +7 C V See Below Industrial - C to +5 C V See Below o C 373 tbl 2a 373 tbl 5 µa ILO Output Leakage Current VDD = Max, = VIH, VOUT = GND to VDD 5 µa VOL Output Low Voltage IOL = ma, VDD = Min V VOH Output High Voltage IOH = ma, VDD = Min 2 V tbl 5

3 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges (1, 2) DC Electrical Characteristics (VDD = Min to Max, VLC = 2V, VHC = VDD 2V) 71VSA 71VSA 71VSA 71VSA2 Symbol ICC ISB ISB1 Parameter Com'l Ind Com'l Ind Com'l Ind Com'l Ind Dynamic Operating Current ma < VLC, Outputs Open, VDD = Max, f = fmax (3) Dynamic Standby Power Supply Current ma > VHC, Outputs Open, VDD = Max, f = fmax (3) Full Standby Power Supply Current (static) ma > VHC, Outputs Open, VDD = Max, f = (3) Unit 1 All values are maximum guaranteed values 2 All inputs switch between 2V (Low) and VDD 2V (High) 3 fmax = 1/tRC (all address inputs are cycling at fmax); f = mea no address input lines are changing 373 tbl 6 AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3V 3 V V See Figure 1 and tbl 7 33V I/O Z =5Ω +V 5Ω DATAOUT 5pF* 32Ω 35Ω 3pF 373 drw drw Figure 1 AC Test Load *Including jig and scope capacitance Figure 2 AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) 62 3

4 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min to Max, Commercial and Industrial Temperature Ranges) 71VSA 71VSA 71VSA 71VSA2 Symbol Parameter Min Max Min Max Min Max Min Max Unit READ CYCLE trc Read Cycle Time 2 taa Address Access Time 2 ta Chip Select Access Time 2 tclz (1) Chip Select to Output in Low-Z tchz (1) Chip Deselect to Output in High-Z toe Output Enable to Output Valid tolz (1) Output Enable to Output in Low-Z tohz (1) Output Disable to Output in High-Z toh Output Hold from Address Change WRITE CYCLE twc Write Cycle Time 2 taw Address Valid to End-of-Write 7 tcw Chip Select to End-of-Write 7 tas Address Set-up Time twp Write Pulse Width 7 twr Write Recovery Time tdw Data Valid to End-of-Write tdh Data Hold Time tow (2) Output Active from End-of-Write twhz (2) Write Enable to Output in High-Z This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested 373 tbl

5 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No 1 (1) taa trc OE toe tolz DATAOUT (3) ta tclz HIGH IMPEDANCE tohz tchz DATAOUT VALID 373 drw 5 (1, 2, ) Timing Waveform of Read Cycle No 2 trc toh taa toh DATAOUT PREVIOUS DATAOUT VALID DATAOUT VALID 373 drw 6 1 WE is HIGH for Read Cycle 2 Device is continuously selected, is LOW 3 Address must be valid prior to or coincident with the later of traition LOW; otherwise taa is the limiting parameter OE is LOW 5 Traition is measured ±2mV from steady state 62 5

6 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No 1 (WE Controlled Timing) (1,2,) twc taw tas (2) twp twr WE twhz tow tchz DATAOUT (3) HIGH IMPEDANCE (3) DATAIN tdw DATAIN VALID tdh 373 drw 7 (1, ) Timing Waveform of Write Cycle No 2 ( Controlled Timing) twc taw tas tcw (3) twr WE DATAIN tdw DATAIN VALID tdh 373 drw 1 A write occurs during the overlap of a LOW and a LOW WE 2 OE is continuously HIGH During a WE controlled write cycle with OE LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp 3 During this period, I/O pi are in the output state, and input signals must not be applied If the LOW traition occurs simultaneously with or after the WE LOW traition, the outputs remain in a high impedance state must be active during the tcw write period 5 Traition is measured ±2mV from steady state 6

7 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Ordering Information 71V H SA XX X X X Device Type Power Speed Package Process/ Temperature Range Blank I Commercial ( C to +7 C) Industrial (- C to +5 C) G Restricted hazardous substance device TY Y PH 3-mil SOJ (SO32-2) -mil SOJ (SO32-3) TSOP Type II (SO32-) 2 Speed in nanoseconds Blank H First generation or current die step Current generation die step optional 373 drw

8 IDT71VSA, 33V CMOS Static RAM 1 Meg (K x -Bit), Center Power & Ground Pinout Commercial and Industrial Temperature Ranges Datasheet Document History 11/22/99 Updated to new format Pg 1, 7 Added Industrial Temperature range offerings Pg 2 Added Recommended Operating Temperature and Supply Voltage table Pg 6 Revised footnotes on Write Cycle No 1 diagram Pg Added Datasheet Document History /3/ Pg 3 Tighten ICC and ISB Pg Tighten AC Characteristics tohz, tow and twhz /22/1 Pg 7 Removed footnote "-mil SOJ package only offered in and speed grade" 11/3/3 Pg 1,3,7 Added Industrial temperature offering speed grade 1/3/ Pg 7 Added "Restricted hazardous substance device" to ordering information 2/1/7 Pg 7 Added H generation die step to data sheet ordering information /13/ Pg 7 removed "IDT" form the orderable part number CORPORATE HEADQUARTERS for SALES: for Tech Support: 62 Silver Creek Valley Road or ipchelp@idtcom San Jose, CA fax: wwwidtcom The IDT logo is a registered trademark of Integrated Device Technology, Inc