UAD2 + Universal Access Device2 plus

Transcription

1 UAD2 + Universal Access Device2 plus The access to the whole choice of C166, XC166, XC2000, XE166, C166CBC, C166S V2, TriCore, PowerPC, ST30, STR7, ARM7, ARM9, ARM11, XScale, SH-2A derivatives is supported with the Universal Access Device 2+, the new all-in-one addon interface hardware for Universal Debug Engine. UAD2+ offers state-of-the-art hardware support for debugging via JTAG/OCDS and via a wide variety of target system access channels. It is optimized for High-Speed Communication between the UDE on the Host PC and a target system. UAD2+ supports all access features of UDE in an optimized manner. Basic Features Standalone Communication device 17 x 14 x 5cm³ Host Connection via USB 2.0 o 480Mbps Communication Speed o USB 1.1 supported with reduced efficiency o Works under Windows 2000, Windows XP and Windows Vista or via Host Connection via IEEE1394-OHCI (also known as Firewire or i.link ) o 400Mbps Communication Speed o Integrated Hub Function for optimal Operating with other IEEE1394Targets o Works under Windows 2000, Windows XP and Windows Vista or via Ethernet (in preparation) o 10/100Mbps Communication Speed o Works under Windows 2000, Windows XP and Windows Vista Galvanically isolated target interfaces minimize the negative effects of potential differences between UAD2+ and the target Build-in JTAG extender technology features a maximal cable length of the JTAG cable between the UAD2+ and the target up to 50 cm (1 meter and longer on request) JTAG port is provided via a dedicated pod with drivers and cables Serial Wire Debug (SWD) support Serial Wire Viewer (SWV) support Instrumentation Trace Macrocell (ITM) support CAN bus D-Sub male connector (CiA pin assignment) as debugging communication channel to C167CR, C164CI, XC161CJ, XC164CS, XC167CI or equivalent ST10 and TriCore CAN target systems On-board high-speed CAN bus interface driver for ISO-DIS standard Automatic firmware update via on-board Flash programming possible Flexible serial high-speed communication to an XC16x, C16x, ST10, ARM7, ARM9 and TriCore target system. Supported microcontroller derivatives C166, ST10 XC166, XC2000, XE166 TriCore PowerPC ARM7, ARM, ARM11 XScale Cortex-M3

2 ASC Interface Universal Access Device 2+ provides a buffered asynchronous communication path between an external RS232 device controlled by the target system application and the ASC0 of the target system controller. In ASC-BSL/CAN, ASC-BSL/3Pin or ASC-BSL/SSC mode, after booting up the target system controller via ASC0 and transferring the monitor code the ASC0 channel will no longer be used by the debug communication and is therefore available for the application. With the buffered ASC0 of Universal Access Device 2+, the application's external RS232 device does not need to be manually reconnected - this is automatically done by Universal Access Device 2+. Additionally to the buffered ASC0 via RS232, an unbuffered TTL-level ASC0 is available. For this, no additional hardware (RS232 driver) at the target system is required - the signal lines TxD and RxD are directly connected to the corresponding controller pins. SSC Interface As no additional hardware is required, the maximum transmission speed of up to 5Mbps can be achieved. RS232/ASC0 for booting-up the target system. After downloading the monitor (<< 1sec at 115kbps), the RS232 interface is available for the application again without any external hardware or application software reconfiguration. About 3kByte of target system RAM for the SSC monitor. Only 3 port pins of the C16x controller used. Optionally one timer for run-time measurement. 3Pin Interface ASC Bootstrap loader / 3Pin Interface - The Perfect Solution for ROMless Debug Monitors With the new ASC-BSL/3Pin (Hardware) interface supported by Universal Access Device 2+, a plug-and-play-like target system access can be achieved. Saving system resources in mind, this interface has been developed to free the RS232/ASC0 and any other controller peripherals that are often used by the application itself while maintaining the advantages of an uploadable high-speed monitor without the need for ROM and programming the ROM at the target system prior to debugging. The target system is connected to Universal Access Device 2+ via a standard RS232 link for downloading the 3Pin target connection monitor and three additional lines for the 3Pin interface. With the ASC-BSL/3Pin interface, a host-to-target communication speed up to of 12 times faster than a standard host PC-COMx based RS232 interface is supported. RS232/ASC0 for booting-up the target system. After downloading the monitor (<< 1sec at 115kbps), the RS232 interface is available for the application again without any external hardware or application software reconfiguration. About 3kByte of target system RAM for the 3Pin monitor. Only 3 port pins of the C16x controller used. Optionally one timer for run-time measurement. Your advantage: No additional hardware has to be set-up - no additional monitor required! CAN Interface The Universal Access Device 2+ supports the CAN communication channel between host PC and target system. Following advantages are thereby achieved:

3 CAN communication channel may be used simultaneously for your application and for debugging because of the CAN bus node addressing. The CAN bus debugging monitor in the target system requires just 4kByte of code and 128Bytes data memory; it can thus be easily integrated into nearly all types of target systems. 4 message identifier and 2 CAN module messages objects for host-to-target communication must be reserved. CAN bus timing is user-definable. The CAN debugging interface uses the on-chip CAN module of the C167CR, C167CS, C164CI, C161CS, C161JS, XC161, XC164, XC167, ST10R167, ST10R168 or TriCore TC1775, TC1130, TC1796 CAN derivatives or an external i82527 CAN bus controller for communication with debugger on the host PC. The Controller Area Network (CAN) bus and its associated protocol allows very efficient communication between a number of stations connected to the CAN bus. Accessing a number of stations simultaneously may be of great advantage when designing complex systems with a number of CAN nodes based on XC16x, C16x, ST10. Other software performance enhancing features of the CAN bus are: The CAN bus debug interface is an excellent solution allowing rapid access to the target system for software development, testing and on-site maintenance at all times. Special CAN Bus Target Monitor Features Target system monitors for XC16x, C16x, ST10 internal on-chip CAN module and external i82527 available. CAN bus ROM monitors for standard evaluation boards come with the Debugger Standard Package. User specific CAN bus monitors can be configured from the UDE-Mon Portable Monitor package. All components (sources, objects and libraries) are compatible with the available C16x / ST10 cross compilers. Standard and Extended Identifiers supported. CAN interrupt sharing between monitor and application using the On-Chip CAN module. Flash programming via CAN bus (internal FLASH and external FLASH-EPROMs AMD 29F xxx) ROM-less CAN debug monitors possible (ASC Bootstrap loader and CAN). CAN Bus Analyzer Independent intelligent subsystem enables continuous trace of CAN bus messages CAN bus observing capability, can also be used in conjunction with the CAN bus based debugger communication CAN bus stimulation - ideally suited for testing CAN applications! The Universal Access Device 2+ CAN Bus Monitoring tool is designed as a development aid for applications using the CAN bus and is not supposed to completely replace a CAN Analyzer. JTAG OnChip Debug Support (OCDS) - The New Debug Interface for Infineon C166CBC, C166S V2 (XC16x) and TriCore Family Microcontrollers supported by Universal Debug Engine with Universal Access Device 2+ represents a new technology of debug support for the Infineon 16- and 32-bit microcontrollers. So far, OCDS functionality has been implemented into the newest C166CBC, C166S V2 derivatives and the new generation 32-bit µc-dsp TriCore architecture. Universal Access Device 2+ supports all of the essential OCDS features like: Standard 16 pin Infineon JTAG/OCDS L1 connector (2.5V - 3.3V I/O ring voltage) supports C166CBC, C166S V2 and TriCore JTAG debug communication channel up to 50 MHz shift clock - download rate up to 3,5 MByte/s Standard 20 pin ARM JTAG connector (2.5V - 3.3V I/O ring voltage) supports ARM7/ARM9 JTAG debug communication channel up to 25 MHz shift clock - download rate up to 1 MByte/s

4 Standard 14 pin PowerPC OnCE connector (2.5V - 3.3V I/O ring voltage) supports Freescale PowerPC OnCE debug communication channel up to 25 MHz shift clock Standard 16 pin PowerPC COP connector (2.5V - 3.3V I/O ring voltage) supports IBM/Motorola PowerPC COP debug communication channel up to 25 MHz shift clock Direct target system access for the host debugger via JTAG interface (IEEE1149.1) OnChip debug operations supports emulator-like additional debug functionality Hardware Code Breakpoints Read or Write Access Data Breakpoints Real-Time Trace Operand Access Using these debug features, no additional hard- or software resources in the target system are required. Therefore, when using the JTAG OCDS L1 port for the debugger all other interfaces of the microcontroller are available to the application with no limitations and the system is ready for debugging over its whole lifetime. Using JTAG OCDS L1 with Universal Debug Engine (UDE) and Universal Access Device 2+ gives the following major advantages: Download performance up to 25 times faster than the low-cost printer port solution! Dramatically speeds up the turn-around cycles of debug sessions, especially of larger applications (1++MByte). No resident target monitor in RAM or ROM required. Hardware breakpoints available for stepping through program code in ROM or OnChip- Flash/OTP. Furthermore, complex trigger conditions can be defined. Symbolic trigger conditions feature now enhanced definitions. With the Universal Access Device 2+, single-chip applications can now be debugged via JTAG OCDS L1 without costly in-circuit emulators. JTAG-Extender The UAD2+ is equipped with an active UAD-JTAG Extender per default and allows a maximal cable length of the JTAG cable between the UAD2+ and the target up to 50 cm (1 meter and longer on request). The UAD-JTAG Extender provides a dedicated JTAG pod with drivers and cables. Supported JTAG Connectors: 16 pin shroud male header - Infineon connector 20 pin shroud male header - ARM connector Customer's connectors on request Cable length 50cm - longer cable length on request Support of open-drain RESET# Target MCU I/O voltage used for I/O operations LVDS technology for highest performance and signal integrity.

5 OCDS L2 Instruction Trace The OCDS L2 trace board is an add-on for the Universal Access Device 2+ and allows the recording of trace information of a running program on the TriCore in real-time. UAD OCDS L2 Trace Add-On Board The system is an optimized solution to support all the features of the Infineon OCDS L2 trace port functionality in the best manner. Trace ports supported up to 170 MHz 1M Sample trace depth Timestamp resolution 1/ f CPU (i.e. 10ns at f CPU =100MHz) 40bit time stamp range Support the full OCDS L1 functionality for providing the trigger events for the tracing unit Intelligent trace filter for optimal trace utilization TriCore and PCP trace Complete support of OCDS L1 trigger signals for trace control and visualization Additional 8 external trace lines to observe peripherals and external signals LVDS interface to external connector pod supports pods for 60 pin OCDS L2 High-Speed Connector (proposed by Infineon) Supported derivatives: TC1130, TC1765, TC1796, TC1910, TC1912, TC Pin OCDS L2 High-Speed Connector Pod Recommended by Infineon to support connection to OCDS L2 port of TriCore 1.3 systems (TC11IB, TC1910, TC1912, TC1920 and future derivatives) Connector system based on SAMTEC 60 pin high-speed connector QSH F-D-A Prepared to use for systems up to 150MHz system clock Supports 2.5 Volt to 3.6 Volt TriCore 1.3 I/O ring voltage 80 pin cable to trace base board using LVDS interface to ensure high trace signal quality UDE Support of OCDS L2 Trace Functions The complete utilization of trace functionality by 4 setup modes: 2 standard modes to allow easy access to standard trace tasks 2 expert modes to allow full access to complex possibilities of trace system Full connection of trace setup to symbolic reference of source code Visualization of internal and external trace events Browse capability between trace output and C-language sources

6 ETM and ETB Trace for ARM7 and ARM9 The ARM7 and ARM9 ETM trace board is an add-on for the Universal Access Device 2+ and allows the recording of trace information of a running program on the ARM derivatives in real-time. UAD ARM7 and ARM9 ETM Trace Add-On Board The system is an optimized solution to support all the features of the ARM ETM trace port functionality in the best manner. Trace ports supported up to 170 MHz, 4 or 8 bit width Halfrate Clock Mode supported 1M Sample trace depth Timestamp resolution 1/ f CPU (i.e. 10ns at f CPU =100MHz) 40bit time stamp range Support the full ETM functionality for providing the trigger events for the tracing unit Intelligent trace filter for optimal trace utilization Additional 8 external trace lines to observe peripherals and external signals LVDS interface to external connector pod supports pods for 38 pin ETM Mictor High-Speed Connector (proposed by ARM) Supported derivatives: LPC21xx, AT91RM Pin ARM7 and ARM9 Mictor High-Speed Connector Pod Recommended by ARM to support connection to ARM ETM Connector system based on Mictor 38 pin high-speed connector Prepared to use for systems up to 170MHz system clock Supports 2.5 Volt to 3.6 Volt I/O ring voltage 80 pin cable to trace base board using LVDS interface to ensure high trace signal quality UDE Support of ETM Trace Functions The complete utilization of trace functionality by setup modes: 1 standard mode to allow easy access to standard trace tasks Full connection of trace setup to symbolic reference of source code Visualization of internal and external trace events Browse capability between trace output and C-language sources UDE Support of ETB Trace Functions The Embedded Trace Buffer (ETB) extends the ETM unit of ARM derivatives by an embedded onchip circular trace buffer. This simplifies the adaptation of external trace units because the high speed trace signaling does not need to transfer to the external unit. The trace buffer is managed and read via the JTAG communication channel. Supported derivatives: LPC3000 derivatives

7 DAP Support for Infineons TriCore and XC2000 The Device Access Port DAP, a new debug interface was established by Infineon for the AUDO Future, XC2000M, XE166M devices and other upcoming 16-bit and 32-bit-microcontrollers. The 2-wire or 3-wire DAP allows debug communication with higher transmission rates than existing JTAG based communication channels. The new board connector is a 0.05 inch double row 10-pins microterminal with keying shroud, which saves board space on targets system side. UDE Support for DAP High-speed downloading via DAP is achieved by the communication devices UAD2 and UAD2+, the hardware addons of the Universal Debug Engine. DAP communication 50 MHz Transfer rate up to 3,5 MByte/s ( with TC1797 AUDO Future) 2-wire/pin and 3-wire/pin DAP mode supported Prepared for single-wire/pin DAP mode LED for power indicating UAD DAP Extender with LVDS The UAD2+ with DAP Extender uses the LVDS technology and a galvanically isolated interface for highest performance and signal integrity of the DAP interface. It allows interface cable length of up to 2 meters SWD Support for Cortex The Serial Wire Debug (SWD) interface or Serial Wire Debug Port (SW-DP) is one of the features of the debug and trace technology ARM CoreSight. First implementations of SWD are realized in the derivatives of the Cortex-M3 core Stellaris of Luminary Micro (now Texas Instruments) and in the derivatives of the STM32 family by STMicroelectronics. The known JTAG Debug Port (JTAG-DP) is supported furthermore. Both debug ports, the SWD and the alternative JTAG debug port can be combined to the Serial Wire JTAG Debug Port (SWJ-DP), the CoreSight standard port. When using SWD, the TDO signal can provide trace event messages via the Serial Wire Output (SWO). This behaviour can be used by the Serial Wire Viewer (SWV) to output system events via a single pin: Instrumentation trace ITM (printf-like Debugging) Watchpoint Trace DWT, Instruction Pointer Trace Event Trace (Interrupts) UDE Support for SWD Target connection via SWD is achieved by the communication devices UAD2 and UAD2+, the hardware add-ons of the Universal Debug Engine and the additional UAD2 SWD adapter. UAD SWD Extender with LVDS The UAD2+ in touch with the Extender and the SWD adaptor uses the LVDS technology and a galvanically isolated interface for highest performance and signal integrity of the SWD interface. It allows interface cable length of up to 2 meters.

8 Electrostatic Precautions Electrostatic Discharge (ESD) can damage a sensitive electronic component! Under several conditions static electricity and ground potential differences between the Access Device and the user's target hardware can build up high voltages - over Volts (10 kv) in some cases. The electrostatic discharge of this build-up voltage results in fast high current waveforms and fast magnetic (H-field) or electrostatic (E-field) disturbances. The discharge into the electronic components and circuitry can damage or destroy hardware components, resulting in failures and reduced reliability. Because of the non-hot-pluggable 3.3 Volts / 5 Volts - TTL properties of the JTAG and the 3Pin/Serial connectors, these ports are endangered especially. The maximum voltage on these pins may not exceeded 5.5 Volts against the UAD s ground, especially in the case that the ground planes are not connected first. To protect your hardware against damage from static electricity and ground potential discharge, you should follow some basic precautions: 1. Before you change any cable connections from the Access Device, please remove the power from the Access Device and your target system. 2. Please ensure that the static electricity and ground potentials between the Access Device, the host PC and the target hardware are balanced. If there is a danger of high potential differences, you must connect the Access Device, the host PC and the target hardware to the same ground domain via a low resistance connection. 3. Establish the target connection and power on the systems. In all cases, the following rule must be attended: The first connection between the devices must be done via the ground! Solution All Universal Access Devices are equipped with a ground socket on the front side. Please use this ground socket for discharging the static electricity and balancing ground potentials between the Universal Access Device, the host PC and the target hardware BEFORE you connect the target hardware to the Access Device. The UAD2+ contains protection function already. Please note, that these protection functions DOES NOT suspend the precautions described above.