Making Informed Memory Choices FTF-IND-F0378

Transcription

1 Making Informed Memory Choices FTF-IND-F0378 Freescale Technology Forum Jim Cooke Mike Kim April 10, Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 1

2 Memory Agenda Non-Volatile Memory Choices DRAM Choices Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program 2

3 NVM architectures NOR Each memory cell can be accessed independent of the others Physical "contact" to each memory location NAND Memory cells are grouped in stacks called strings Physical contacts to the cells are reduced resulting in better cell efficiency NOR Advantages NAND Advantages Direct to read circuitry D G S D G S "bitline" Fewer litho transitions Broad portfolio (Mb-Gb) Good read performance execute In Place capable True random access Easier to design Lowest cost under128mb Assumed higher quality Fewer litho transitions Broad portfolio (Gb 1Tb) Good sequential performance Lowest cost at high densities Challenges to use RAW MAMD Simple when paired with a controller, like emmc G G G G D S D S D S D S Direct to read circuitry 3

4 Single Level Cell vs. Multi-Level Cell SLC 1 physical bit = 1 data bit Cell either programmed or erased Higher performance SLC NAND more reliable than MLC NAND MLC 1 physical bit = 2 data bits 3 bit per cell technology for some NAND Cells partially programmed Lower performance Higher density and lower cost per MB 4

5 NOR product attributes Simple command sets Cost effective at low densities Stable architectures Value added features (XiP, security, quality, small data, etc) Serial Low pin counts Easy PCB routing Smallest footprint Synchronous operations Cheapest low density Parallel Basic add/data interface Asynchronous random access Synchronous burst operations Higher throughput Best XiP architecture 5

6 NAND product attributes Low pin counts Lowest cost/bit at high densities Frequent conversions/migrations required at higher densities Fast programming Discrete Some processors support boot Some standards (ONFI) Common packages Needs SW for file / error management Wide density range (128Mb-1Tb) Managed Standards (emmc, USB, usd ) Error management onboard OS File system (looks like drive) Some processors support boot Higher densities (4-64GB) Easier conversions/migrations 6

7 NAND technology challenges How to manage the ECC requirements? NAND controllers with high ECC capability ECC NAND managed solutions on-die ECC Fully managed solutions emmc, eusb, others How to manage lower Endurance? Understand the application and usage model How does the file system work? How often are you programming? How big is the data file/s? What is the PLC of your system? Determines PE Cycles and Density Required Intersecting your project and the memory technology is key to success! 7

8 NAND system solutions for Industry Raw NAND for application expert with NAND data Host Controller I management and ready to support ECC needs. NAND Interface FTL ECC LLD NAND BUS Raw NAND ECC NAND for application that do not want to change the ECC with the NAND litho shrink. Host Controller II NAND Interface FTL LLD NAND BUS ECC NAND ECC Serial NAND for application requiring high density with Serial protocol. Host Controller III SPI Interface FTL LLD SPI BUS SPI ECC emmc interface for application that want to offload by any NAND data management with a standard interface. Host Controller IV emmc Interface LLD MMC BUS emmc NAND ECC FTL eusb interface for application that want to offload by any NAND data management with a standard interface. Host Controller V eusb Interface LLD USB BUS eusb NAND ECC FTL LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling 8

9 Level of Management by NAND solutions Level of Management by NAND Solution Raw NAND ECC NAND (On-Die ECC) Fully Managed (emmc, eusb) Complexity of Customer Development (NAND Management by Host) New Product Qualification (Complexity & Effort) High Med Low High Med Low Relative Cost Low Med Med + Trade offs between Complexity, Qualification Effort & Cost 9

10 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Choices Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program 10

11 DRAM product attributes Many different types Fast read performance Fast writes Leading edge requires many conversions Discrete Common standards Common packages Many levels in a single system Module Higher density reach Easier conversions/migrations Standards and custom options ECC management enabled 11

12 DRAM Selection Criteria Which DRAM technology(ies) are supported or planned by the processor? Proto/Production timeframe & expected life support needs? How many gigabytes are needed by the app? What is the memory bus width? Is ECC required for the DRAM? How much bandwidth (MB/sec) is needed by the app? Are there any preferred packages (discrete or module)? Does the customer require upgrade/cost reduction path (higher density/litho transition)? 12

13 PC Speed Trend Typical 1yr Speed Cadence Interrupted High End V V V V V V Main Stream -800/ V V V/1.35V V -1600/ V/1.20V -1600/ V/1.20V Value Technology DDR2/DDR3 DDR3 DDR3 DDR3/DDR4 DDR3/DDR4 DDR3/DDR4 Use PC trend to find price sweet spot DDR4 enables the performance and power improvement 13

14 LPDDR/DDR technology comparisons 14

15 Technical Notes Power calculator ( TN DDR2 (point to point) package sizes and layout basics. TN Calculating Memory System Power for DDR2 TN Design guide for Two-DIMM, unbuffered systems (DDR2) TN DDR3 point-to-point design support E0593E20 Technical Note: New function of DDR2 SDRAM On die termination (ODT) TN DDR3 point to point design support TN Design guide for two DDR UDIMM systems TN Calculating Memory System power for DDR3 15

16 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program 16

17 Density Needs for Boot Memory Low Density Mid Density High Density 0.5Mb 128Mb 1 Gb 2 Gb 4 Gb 8 Gb 2GB 16 GB 64GB SPI NOR 0.5Mb to 1Gb Parallel NOR 32Mb to 2Gb SLC NAND Small Page 128Mb to 512mb Low Density SLC 1Gb to 4Gb High Density SLC 8Gb to 128Gb MLC NAND 16Gb to 512 Gb Managed NAND emmc 4GB to 64GB eusb 2GB to 16 GB 17

18 Solutions for different requirements NOR vs. NAND Lowest Floor Cost ($) Lowest $/GB Serial NOR Parallel NOR SLC NAND Managed NAND MLC NAND Longer lifecycles Ease of use Diverse products Lower Floor cost Code, Code+Data Shorter lifecycles Focus on cost/gb Expanding markets Mostly Data Focused Customer Requirements Dictate the Solution 18

19 Performances consideration for system solutions Host Controller I Raw NAND NAND Interface FTL ECC LLD NAND BUS Host Controller II NAND Interface FTL LLD NAND BUS On-Die ECC NAND ECC Host Controller III emmc emmc Interface LLD emmc BUS ECC FTL Device Throughput Raw NAND, ECC NAND and emmc require different management software The correct performance evaluation is at system LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling 19

20 Performances consideration for system solutions Host Controller I Raw NAND NAND Interface FTL ECC LLD NAND BUS Host Controller II NAND Interface FTL LLD NAND BUS On-Die ECC NAND ECC Host Controller III emmc Interface LLD emmc BUS emmc ECC FTL Device Throughput Raw NAND, The evolution of emmc 5.0 (400MT/s PHY) improves performance capabilities LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling 20

21 Flash Architectures Component Level NOR NOR All architectures have their advantages Trend in the industry moving toward the lower pin count architectures 21

22 Performance Comparison Small Data 22

23 Performance Comparison Large Data 23

24 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program 24

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26 Micron Product Longevity Program (PLP) Micron s PLP addresses customer needs to: Protect their design investments by ensuring a minimum of 10 years of availability on mainstream memory devices Provide stability to existing designs by offering a 2-year conversion timeline in the event of a part-number change (e.g. die shrink) Micron s full product portfolio supported via normal roadmaps: No change to standard products PLP products are a subset of the Micron portfolio Micron s customers now have a choice: Buy standard products with existing service and support OR Buy PLP products to obtain increased longevity and stability 26

27 Micron s Product Longevity Program Automotive Industrial Multi-Market Micron is focused on markets requiring long lifecycles: Automotive, industrial, medical Micron s PLP benefits: 10-year longevity from PLP introduction date 2-year conversion timeline: 1-year LTB (last-time buy) + 1-year LTS (last-time ship) from PTN (product-termination notification) date 27

28 Micron Has a Proven Track Record Micron has a history of supporting memory products for long periods of time and we intend to continue this with PLP! 28

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30 Line Card PLP products are High-volume runners Purchased by large numbers of customers Suitable for automotive, industrial, medical, and other applications requiring 10-year longevity PLP Line Card is a subset of the entire Micron portfolio Not all product families and densities are represented 30

31 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program 31

32 What s next? Customers 1. Understand memory usage 2. Understand true cost 3. Work with a trustworthy supplier Suppliers 1. Provides technology leadership & product longevity 2. Architecture transparency 3. Systems expertise & silicon/solution standards 32

33 Broadest Portfolio Industry s broadest portfolio Computing, server/networking, embedded, mobile, consumer Manufacturing Expertise/Stability Automotive Storage Graphics / Consumer Networks Server Wireless Personal Computing Industrial 33

34 Micron s Product Portfolio NOR Parallel and Serial NOR product portfolios, densities 512Kb-2Gb+ Technology leadership on 65nm and 45nm. Automotive and industrial qualified solutions NAND Discrete and managed solutions, densities 128Mb-64GB Technology leadership on 20nm Automotive and industrial qualified e MMC solutions Legacy support for low density NAND 34

35 DRAM Micron s Product Portfolio Legacy SDRAM through cost/performance leading DDR3/4 offerings Discrete and module DRAM solutions High speed RLDDRx Options Automotive and industrial qualified solutions 35

36 Working with industry leaders Architecture alignment Industry standards Reference designs Co-marketing Board support package Schematic reviews Third-party enablement Debug services Software solutions Strategic initiatives Micron is your trusted advisor 36

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38 RiOT Board Example Two 4Gb DDR3 DRAM s Micron Confidential 2012 Micron Technology, Inc. 38

39 4GB emmc Micron Confidential 2012 Micron Technology, Inc. 39

40 Tower Plug In (TWRPI) 40