Integrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC

Transcription

1 Integrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC 2012 The MathWorks, Inc. 1

2 Agenda Integrated Hardware / Software Top down Workflow for Zynq, highlighting: Automatic Code Generation: HDL code generation for the FPGA fabric and C-Code generation for the ARM MCU Automatic Interface Logic Generation: Generation of the interface logic and software between the FPGA and ARM. Integrated Verification: Integrated HDL Verification using HDL Co-simulation and FPGA-in-Loop Q&A 2

3 Demo - Zynq Model-Based Design Workflow 3

4 Who is Who??? Who is a System Engineer? Who is an FPGA/ASIC designer? Who is using MATLAB? Who is using Simulink? Who is converting MATLAB to C or HDL? 4

5 Algorithm Development Process Requirements Research & Design Explore and discover Design Gain insight into problem Evaluate options, trade-offs Implementation Elaborate Test Test & Verification Desktop.dll.exe.c, C,.cpp C++ Embedded C, C++ VHDL / Verilog Structured Text Design Elaborate Test 5

6 You May Have Some Questions? Can I generate HDL and C code from my MATLAB and Simulink models? Can I generate integrated test-bench to co-simulate it with HDL Simulators? Can I Generate the interface logic? What about porting it on SoC FPGA and verifying the DUT with the golden MATLAB/Simulink test-bench? And Many more questions 6

7 Solution: C and HDL Code Generation Design, execute, and verify algorithms in MATLAB MATLAB Algorithm Design Automatically generate C or HDL code Deploy generated code on hardware MATLAB Coder CGenerate HDL Coder Generate VHDL/Verilog FPGA MCU ASIC DSP FPGA ASIC 7

8 The Algorithm Design Challenge How can we: Implement designs on SoC FPGA s? MATLAB/Simulink Algorithm Design Partition the HW and SW? Generate the Interface Logic? FPGA MCU SoC ASIC DSP FPGA s ASIC 8

9 What is SoC FPGA s? ARM Processor Interface FPGA FPGA + ARM on one chip Enables high-performance system development Reduces cost over multi-chip solutions 9

10 Design Challenge ARM Processor C-Code Software Typically programmed in C Often runs a Linux operating system Well-established workflows exist CHALLENGES FPGA Designers not familiar with programming processors What should run on the processor vs. the FPGA? 10

11 Design Challenge FPGA HDL Code Hardware Typically programmed in VHDL/Verilog Established workflows exist CHALLENGES DSP/Processor programmers not familiar with FPGA Design What should run on the FPGA vs. the processor? 11

12 Design Challenge Interface CHALLENGES No established rules for hooking up the interface Different versions of AXI interface for different bandwidth requirements Zynq uses standard AXI4 interface between FPGA and ARM 12

13 How can I address these challenges Model-Based Design provides a single environment from requirements to prototype A guided workflow for hardware and software development 13

14 Model-Based Design 2012 The MathWorks, Inc. 14

15 Why Model-Based Design? Requirements Development Simulation Code Generation Continuous Verification 15

16 Model-Based Design: From Concept to Production RESEARCH REQUIREMENTS DESIGN Environment Models Physical Components Algorithms IMPLEMENTATION TEST & VERIFICATION Model multi-domain systems Explore and optimize system behavior in floating point and fixed point Collaborate across teams and continents Generate efficient code Explore and optimize implementation tradeoffs C, C++ VHDL, Verilog ARM INTEGRATION FPGA Automate regression testing Detect design errors Support certification and standards 16

17 Design Challenges ARM Processor C-Code Software Interface FPGA HDL Code Hardware FPGA Designers not familiar with programming processors DSP/Processor programmers not familiar with FPGAs What should run on the FPGA vs. what should run on the ARM? No established rules for hooking up the interface between FPGA and ARM processor 17

18 High-Level Zynq Design Flow RESEARCH Software Model Embedded Coder ARM DESIGN Top-Level System Model IMPLEMENTATION REQUIREMENTS Hardware Model HDL Coder FPGA Zynq Template Xilinx Embedded System Integration Real-Time Parameter Tuning and Verification User defines partitioning MathWorks automates code and interface-model generation MathWorks automates the build and download through the Xilinx tools 18

19 Model-Based Design for Zynq RESEARCH REQUIREMENTS DESIGN Embedded Coder C, C++ C, C++ Environment Models Physical Components Algorithms IMPLEMENTATION VHDL, Verilog ARM DSP FPGA ASIC HDL Coder VHDL, Verilog Structured Text PLC TEST & VERIFICATION FPGA Boards ASIC INTEGRATION Zynq 19

20 Demo - Zynq Model-Based Design Workflow 20

21 Model-Based Design flow using Simulink from Algorithm to FPGA Implementation MATLAB and Simulink Algorithm and System Design DESIGN HDL Coder RTL Creation HDL Verifier HDL Co-Simulation Algorithm Development MATLAB Simulink Stateflow RTL Back Annotation Implement Design Verification Synthesis Functional Simulation Map Static Timing Analysis Place & Route Timing Simulation HDL Verifier FPGA in the Loop 21

22 Verification Landscape: Model VHDL / Verilog FPGA Requirements Functional Equivalence Coverage Property Proving Virtual Platforms Requirements Equivalence Coverage Assertions Equivalence Regression Timing Analysis 22

23 Verification Challenges: Stimuli-Driven Test Bench in HDL Simulators Digital waveforms are difficult to analyze Application specific analysis methods are needed How to get test vectors to achieve 100% test coverage? Formal methods to derive required test cases 23

24 HDL cosimulation to verify HDL Re-use System Level Test Bench for HDL Verification Re-use test benches for equivalence checking Integrate with HDL code coverage analysis HDL Cosimulation Flexible test bench creation: closed loop, multi domain Also works with handwritten code Integrate with Modelsim/Questa and Incisive 24

25 Verification Landscape Solution: Re-use System Level Test Bench Model VHDL / Verilog FPGA Requirements Functional Equivalence Coverage Property Proving Virtual Platforms Requirements Equivalence Coverage Assertions Equivalence Regression Timing Analysis 25

26 Demo - Zynq Model-Based Design Workflow 26

27 Zynq Model-Based Design Workflow MATLAB and Simulink Algorithm and System Design AXI FPGA AXI ARM 27

28 Zynq Model-Based Design Workflow MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW Simulink Model HDL IP Core Generation AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core 28

29 Zynq Model-Based Design Workflow HDL IP Core Generation MATLAB and Simulink Algorithm and System Design AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink Programmable Logic IP Core External Ports EDK Integration EDK Integration FPGA Bitstream Zynq Platform Processing System AXI4-Lite AXI Video DMA AXI Lite Accessible Registers AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports Programmable Logic IP Core EDK Project 29

30 Zynq Model-Based Design Workflow MATLAB and Simulink Algorithm and System Design HW HDL IP Core Generation SW EDK Integration SW Interface Model Generation Simulink Model SW Interface Model Generation FPGA Bitstream Zynq Platform SW Build SW I/O Driver Blocks SW SW Interface Model 30

31 Zynq Model-Based Design Workflow HDL IP Core Generation EDK Integration MATLAB and Simulink Algorithm and System Design SW Interface Model Generation Real-time Parameter Tuning and Verification External Mode Processor-in-the-loop FPGA Bitstream SW Build Zynq Platform External Mode PIL 31

32 Zynq in Action Ball Tracking Demo Video stream filtered to find and mark greenish ball FPGA (HW): Ball Tracking ARM (SW): Draw marker Camera HDMI IN Ball Tracking Coordinates DDR3/ VDMA Video Mark Motor Motor Control Desired Position ARM Processor FPGA 32

33 AXI4-Lite Fast Prototyping and Iteration Fast prototyping, iteration, and live probing/tuning directly on Zynq hardware TCP/IP AXI4-Lite Blocks IP Core Registers C Algorithm ARM Cortex-A9 MP (Running Linux) FPGA IPCore 33

34 Abstraction is Key AXI4-Lite Interface AXI4-Lite AXI Lite Accessible Registers Processor AXI Video DMA AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports FPGA IP Core AXI4-Stream Interface 34

35 Abstraction is Key Focus on algorithm and system design Stay on higher level of abstraction AXI4-Lite Interface Automatic code generation and HW/SW integration AXI4-Lite AXI Lite Accessible Registers Processor AXI Video DMA AXI4-Stream Video In AXI4-Stream Video Out Algorithm from MATLAB/ Simulink External Ports FPGA IP Core AXI4-Stream Interface 35

36 AXI4-Lite Bus Embedded System Integration Zynq HW/SW Co-design Workflow Summary HW Design SW IP Core Generation AXI Lite Accessible registers FPGA IP Core Algorithm from MATLAB and Simulink External Ports Simulink Model SW I/O Driver Blocks SW Generate SW Interface Model Processor AXI Lite Accessible registers FPGA IP Core Algorithm from MATLAB and Simulink External Ports SW Interface Model Embedded System Project SW Build FPGA Bitstream 36

37 Thank You! 37