PCIe-20AO8C500K. 20-Bit 8-Output 500KSPS Precision Wideband. PCI Express Short-Card Analog Output Module
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1 PCIe-20AO8C500K 20-Bit 8-Output 500KSPS Precision Wideband PCI Express Short-Card Analog Output Module Features Include: Eight Single-ended or 3-Wire Differential 20-Bit analog output channels. Simultaneous Clocking; Individual R-2R 20-Bit DAC per output channel. Clocking rates from zero to 500KSPS. Software-selectable fullscale output ranges: ±10V and ±5V; Optionally ±5V and ±2.5V. 256K-sample output FIFO buffer. Low Glitch Impulse; Typically 3.8nV-Sec on ±5V range. Low-Noise DACs and output sections produce 95dB SNR. Clocking from either external or internal sample rate generator. Hardware trigger and clock I/O for multiboard synchronization; Selectable as LVDS or TTL. 8 Bidirectional TTL Digital I/O lines. Conforms to PCI Express Specification revision 1.0a. Optional Outputs Disconnect feature supports multiple card redundancy, and ensures quiet outputs during autocalibration. Standard PCI Express Short-Card form factor. Same pinout as that used for the PCIe-18AO8, with similar software interface. Available also in 16-Channel configuration in full-length format. DMA Engine supports block-mode and demand-mode transfers. Remote ground sensing to minimize single-ended errors. On-demand autocalibration of all channels. Applications: Precision Voltage Source Acoustic Research Waveform Synthesis Audio Synthesis Process Control Industrial Robotics REV:
2 FUNCTIONAL DESCRIPTION PCIe-20AO8C500K Preliminary The PCIe-20AO8C500K is a precision 20-Bit analog output product that provides eight simultaneously clocked output channels in a PCI Express short-card form factor. Outputs can be clocked at rates up to 500 KSPS per channel, and are supported by a 256K-Sample FIFO data buffer. Both continuous and burst clocking modes are supported, and voltage ranges are softwareselectable as ±10V and ±5V, or optionally as ±5V and ±2.5V. Clocking and triggering rates can be derived from an internal rate generator, or from external clock and trigger sources to support the synchronous operation of multiple boards. Each analog output channel implements a weighted-dac R-2R configuration, which minimizes latency and has no minimum clocking rate. The outputs can be software-configured for singleended operation or for 3-wire differential operation. An optional outputs-disconnect feature ensures quiet outputs during autocalibration, and supports multiple-card redundancy. On-demand autocalibration determines and applies error correction for all output channels. Eight bidirectional digital I/O lines are programmable as inputs or outputs. Analog Outputs (8) Outputs Disconnect Autocalibration Loopback 8 AO, 8 DIO, Sync I/O System I/O Conn Voltage Reference COMPARATOR Test Data External Clock and Sync I/O; Digital I/O 20-Bit DAC (8) PCIe Conn Host Conn +3.3/+12VDC Power Conversion PCI Express Interface Adapter Regulated Power Voltages Local Bus Local Controller Figure 1. PCIe-20AO8C500K; Functional Organization This product is functionally compatible with the PCI Express Specification revision 1.0a. System input/output connections are made at the front panel through a high-density 68-Pin connector. Power requirements consist of +3.3 VDC and +12 VDC in compliance with the PCI Express specification, and operation over the specified temperature range is achieved with conventional air cooling. 2
3 PERFORMANCE SPECIFICATIONS At +25 O C, with specified operating voltages Analog Output Parameters: Configuration: Voltage Ranges: Output Resistance: Output protection: Loading: Line Imbalance: Signal/Noise Ratio (SNR): Glitch Impulse: Eight simultaneously clocked analog output channels with a dedicated 20-Bit R-2R DAC per channel. Software-selectable as either 2-wire single-ended outputs, or as 3-wire balanced differential outputs. Four-Channel version also available. Software-selectable as ±10V and ±5V, or optionally as ±5V and ±2.5V. Without outputs-disconnect: 1.0 Ohm max at I/O connector pins. With outputs-disconnect: 3.0 Ohms max when connected, 10K min when disconnected. Withstands sustained short-circuiting to ground Zero to ±5ma per channel. Stable with any load capacitance up to 20,000 PFD. (With optional 3-Wire differential output configuration) ±15mV max. 95dB typical on ±10V range; 10Hz - 250kHz. 3.8 nv-s, typical on the ±5V range Transfer Characteristics: Resolution: Output Access: DC Accuracy: (Max error, no-load) 20 Bits ( percent of FSR) 256 K-Sample FIFO buffer. High Range Set; ±10V, ±5V S.E. Range S.E. Zero Accuracy S.E. ±Fullscale Accuracy ±10V ±0.6mV ±1.7mV ±5V ±0.4mV ±1.2mV Diff Range* Diff Zero Accuracy Diff ±Fullscale Accuracy ±10V ±1.5mV ±4.5mV ±5V ±1.2mV ±3.0mV Low Range Set; ±5V, ±2.5V S.E. Range S.E. Zero Accuracy S.E. ±Fullscale Accuracy ±5V ±0.5mV ±1.6mV ±2.5V ±0.4mV ±1.1mV Diff Range* Diff Zero Accuracy Diff ±Fullscale Accuracy ±5V ±1.2mV ±2.7mV ±2.5V ±0.7mV ±1.5mV * Differential output is measured between OUT-XX-HI and OUT-XX-LO. Settling Time: Bandwidth: Crosstalk Rejection: Integral Nonlinearity: Differential Nonlinearity: 8us to 0.1 percent of step, typical with halfscale step, no-load. Typically -3dB at 250kHz 95 db minimum, DC-100 khz ±0.002 percent of FSR, maximum ± percent of FSR, maximum 3
4 Operating Modes and Controls Output Data Buffer: Sample Clock Sources: Triggering Sources: Clocking Modes: Internal Rate Generator: Low-Pass Filter: External Sync I/O: Outputs Disconnect: Output Data Format: 256 K-sample FIFO Internal rate generator; External Clock I/O, Software clock. 500kHz max. Internal rate generator, TTL external trigger I/O, Software trigger. Continuous or periodic. Supports triggered functions. Programmable from 3 to 500,000 output clocks per second. Divides Master Clock frequency to clocking rate using a 24-bit divider. Fixed-frequency 3rd-order low-pass Butterworth filter for each output channel. Enabled or disabled through software. Standard cutoff frequency: 100kHz. Front-panel: Clock and trigger, software-selectable as TTL or LVDS. Internal Connector: Clock and trigger, software-selectable as TTL or LVDS. All outputs can be disconnected from the system I/O connector under software control. This feature has no effect on autocalibration or selftest operations. 20 Bits, selectable as offset binary or two's complement coding, with attached end-of-function flag and channel number. Remote Ground Sense (Single-ended outputs only; See ordering options): Single input to correct for differences in ground potentials between single-ended outputs and their loads. Accuracy: ±1% (E.g.: 100mV potential difference is corrected to within ±1mV). Input impedance: 5K ±0.1K Compliance (range): ±1.0V. Bandwidth: 600 Hz, typical. If not used, may be left disconnected or connected to OUT xx RTN. Digital Input/Outputs: Eight TTL I/O lines in two groups of four bits, group-configurable as inputs or outputs. 0.2ma maximum input loading as current source, 8ma output loading as either source or sink. Direct register control. PCI Express Compatibility: Conforms to PCI Express Specification revision 1.0a. DMA transfers as bus master with two DMA channels. Power Requirements: +3.3VDC ±0.2 VDC from the PCIe bus, 0.9 Amps typical, 1.0 Amps maximum. +12VDC ±0.4 VDC from the PCIe bus, 0.5 Amps typical, 0.6 Amps maximum. Total power consumption: 9.4 Watts typical, 11 Watts maximum. Physical Dimensions (PCI Express short card): Height: mm (4.37 in) Width: 18.7 mm (0,74 in) not including bracket mm (0.85 in) with Bracket. Depth: mm (6.60 in) 4
5 Environmental Specifications: Ambient Temperature Range: Standard Temperature: Operating: 0 to +70 Degrees Celsius * Storage: -40 to +85 Degrees Celsius Extended Temperature: Operating: -40 to +80 Degrees Celsius * Storage: -40 to +85 Degrees Celsius * Air temperature at board surface. Relative Humidity: 0 to 95%, non-condensing Altitude: Cooling: Operation to 10,000 ft. Conventional air cooling; 150 LFPM Ordering Information: Specify the basic product model number followed by an option suffix "-A-B-C-D-E-F", as indicated below. For example, model number PCIe-20AO8C500K-8-10V M-NOD-0-0 describes a PCI Express short card with eight output channels, ±10V and ±5V output ranges, a MHz master clock frequency, no outputs disconnect, Pin A33 grounded, and standard low-pass filter. Table 1. Ordering Options Optional Parameter Value Specify Option: Number of Channels: 8 output channels A = 8 4 output channels A = 4 Output Ranges: Software-selectable ±10V, ±5V Output Ranges B = 10V Software-selectable ±5V, ±2.5V Output Ranges B = 5V Master Clock Frequency 1 Standard MHz C= M Custom frequency (Mhz) C= xx.xxxm Output Disconnect: With outputs disconnect feature D = OD No outputs disconnect D = NOD I/O Pin A33 Function Output Return 2 E = 0 or NGS Remote ground sense input E = GS Low-Pass Filter Standard cutoff frequency = 100kHz F = 100K or '0' Custom Frequency 3 1 Contact factory for custom frequencies from 47MHz to 53MHz. Typical stability 25PPM. 2 For full I/O compatibility with the PMC/PCIe-18AO8 product, Pin A33 is Output Return kHz to 500kHz, ±12-15%. Contact Sales for availability of specific frequencies. F = xxxk 5
6 SYSTEM INTERFACE CONNECTORS Table 1. System I/O Connector ROW-A ROW-B PIN SIGNAL PIN SIGNAL 1 OUT 00 LO 1 DIGITAL RTN 2 OUT 00 HI 2 DIGIO 00 3 OUT RTN 00 3 DIGITAL RTN 4 OUT RTN 00 4 DIGIO 01 5 OUT 01 LO 5 DIGITAL RTN 6 OUT 01 HI 6 DIGIO 02 7 OUT RTN 01 7 DIGITAL RTN 8 OUT RTN 01 8 DIGIO 03 9 OUT 02 LO 9 DIGITAL RTN 10 OUT 02 HI 10 DIGIO OUT RTN DIGITAL RTN 12 OUT RTN DIGIO OUT 03 LO 13 DIGITAL RTN 14 OUT 03 HI 14 DIGIO OUT RTN DIGITAL RTN 16 OUT RTN DIGIO OUT 04 LO 17 DIGITAL RTN 18 OUT 04 HI 18 DIGITAL RTN 19 OUT RTN CLOCK INPUT LO 1 20 OUT RTN CLOCK INPUT HI 1 21 OUT 05 LO 21 DIGITAL RTN 22 OUT 05 HI 22 DIGITAL RTN 23 OUT RTN CLOCK OUTPUT LO 1 24 OUT RTN CLOCK OUTPUT HI 1 25 OUT 06 LO 25 DIGITAL RTN 26 OUT 06 HI 26 DIGITAL RTN 27 OUT RTN TRIGGER INPUT LO 1 28 OUT RTN TRIGGER INPUT HI 1 29 OUT 07 LO 29 DIGITAL RTN 30 OUT 07 HI 30 DIGITAL RTN 31 OUT RTN TRIGGER OUTPUT LO 1 32 OUT RTN TRIGGER OUTPUT HI 1 33 OUT RTN 07/REM SENSE 2 33 DIGITAL RTN 34 OUT RTN DIGITAL RTN (All output returns "OUT RTN XX' are connected together internally.) 1 (Table 1 and Table 2) Edge-detected LVDS or TTL. When TTL sync I/O is selected, 'HI' pins use TTL signal levels, and 'LO' pins are left disconnected. Software-selected assertion on LOW or HIGH transition. 2 Ordering option; output return or remote ground sense input. Table 2. Internal Sync-I/O Connector PIN SIGNAL 1 AUX CLOCK I/O LO 1 2 AUX CLOCK I/O HI 1 3 DIGITAL RTN 4 DIGITAL RTN 5 AUX TRIGGER I/O LO 1 6 AUX TRIGGER I/O HI 1 a. I/O Connector (panel pin-view) Pin-1 Wire Row B PWB * 34-Conductor Ribbon Cable; in Spacing Cable Connector Row-A Pin 34 I/O Conn Pin 1 Cable-B * Cable-A * Pin-1 Wire Front Panel b. System Cable Connector Figure 2. System I/O Connector System Cable Mating Connector: 68-pin 0.050" Subminiature connector with metal shield: AMP # or equivalent. I/O Connector Installed on Board (Ref): Amp # Recommended Sync-I/O mating cable connector is: Molex# General Standards Corporation assumes no responsibility for the use of any circuits in this product. No circuit patent licenses are implied. Information included herein supersedes previously published specifications on this product and is subject to change without notice. 6
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