VL-PS-COG-C144MVGD-04 REV.A (1.44 CSTN CGA+FPA+BL) JUN/2008 PAGE 2 OF 16 DOCUMENT REVISION HISTORY CHECKED BY DATE DESCRIPTION CHANGED BY

Size: px

Start display at page:

Download "VL-PS-COG-C144MVGD-04 REV.A (1.44 CSTN CGA+FPA+BL) JUN/2008 PAGE 2 OF 16 DOCUMENT REVISION HISTORY CHECKED BY DATE DESCRIPTION CHANGED BY"

Josephine Sparks
6 years ago
Views:

2 PAGE 2 OF 16 DOCUMENT REVISION HISTORY DOCUMENT REVISION FROM TO DATE DESCRIPTION CHANGED BY CHECKED BY A First Release. XIAO LI LAN LUO CHENG

3 PAGE 3 OF 16 CONTENTS Page No. 1. GENERAL DESCRIPTION 4 2. MECHANICAL SPECIFICATIONS 4 3. INTERFACE SIGNALS 7 4. ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS FOR IC ONLY ENVIRONMENTAL CONDITIONS 9 5. ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS TIMING CHARACTERISTICS POWER ON/OFF SEQUENCE POWER FLOW CHART FOR DIFFERENT POWER MODES ELECTRICAL & OPTICAL CHARACTERISTICS CSTN PANEL INSPECTION SPECIFICATIONS REMARK 16

4 PAGE 4 OF 16 VARITRONIX LIMITED Preliminary Specification of LCD Module Type Model No.: COG-C144MVGD General Description 1.44" CSTN, 128 x RGB x 128 dots, 65K, Negative, Transmissive, dot matrix LCD module. Driving scheme: 1/128 duty. Viewing angle: 6 O clock. Driving IC: SITRONIX ST7687S (COG) LCD Controller / Driver or equivalent. Data interface: 8080/6800 system 8-bit parallel bus. Logic voltage: ~2.8V. FPC connection. White LED backlight. RoHS compliance. 2. Mechanical Specifications The mechanical detail is shown in Fig.1 and summarized in Table 1 below. Table 1 Parameter Specifications Unit Outline dimensions 32.36(W) x 53.3(H) x 3.25(D) (Include FPC, the terminal of mm backlight, component area) Viewing area 28.10(W) x 28.20(H) mm Active area 25.49(W) x 26.49(H) mm Display format 128 x RGB x 128 dots Color STN Color configuration RGB stripe x RGB x 128 Dot size (RGB)(W) x (H) mm Dot spacing 0.01 (W) x 0.01 (H) mm Dot pitch (RGB)(W) x 0.207(H) mm Weight TBD gram

5 PAGE 5 OF 16 DISPLAY TYPE DISPLAY RESOLUTION VIEWING ANGLE MUX RATIO & BIAS LCD CONTROLLER/DRIVER LOGIC VOLTAGE LCD DRIVING VOLTAGE OPERATING TEMPERATURE STORAGE TEMPERATURE TYPE COLOR FORWARD VOLTAGE LUMINANCE (cd/m2) (ON THE BACKLIGHT SURFACE) CSTN,65K TRANSMISSIVE 128xRGBx128 6 O' CLOCK 1/128 DUTY, TBD ~2.8V ~14.0V -20 C TO +70 C -30 C TO +80 C LED05: 1pcs LED WHITE TBD MIN. --- TYP MAX. --- BACKLIGHT NC LED+ LED- Vg XV0 V0 Vm VDD VSS VDD NC /CS IF2 IF1 /RST E_RD VDD D D6 D5 D4 D3 D2 D1 D0 RW_WR A0 NC NC Figure 1: Module Specification

6 PAGE 6 OF 16 Vg XV0 V0 Vm VDD VSS /CS IF3 IF1 /RST E_RD RW_WR A0 D0~D7 8 "Sitronix" ST7687S (COG) LCD Controller/ Driver or Equivalent " CSTN LCD PANEL 128 X RGB X 128 DOTS 128 x RGB LED+ LED- WHITE LED BACKLIGHT Figure 2: Block Diagram.

7 PAGE 7 OF Interface signals Table 2(a): Pin assignment Pin No. Symbol Description 1 NC No connection. 2 LED+ Anode of backlight input. 3 LED- Cathode of backlight input. 4 Vg Bias LCD driver supply voltages. Vg OUT is the output voltage of Vg generated by ST7687S. Vg IN is the input pin of power supply to generate Vg voltage for LCD. Vg S is the input pin of power supply to sense the Vg voltage. 5 Vm Vg OUT Vg IN & Vg S should be connected together by FPC. Vm is the I/O pin of LCD bias supply voltage. Voltages should have the following relationship; V0 > Vg > Vm > VSS > XV0. VDDA-0.7V>Vm>0.7V, 2 x VDDA Vg>1.8V When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. 6 XV0 Negative LCD driver supply voltages. XV0 OUT is the output voltage of XV0 generated by ST7687S. XV0 IN is the input pin of power supply to generate XV0 voltage for LCD. XV0 S is the input pin of power supply to sense the XV0 voltage. XV0 OUT XV0 IN & XV0 S should be connected together by FPC. 7 V0 Positive LCD driver supply voltages. V0 OUT is the output voltage of V0 generated by ST7687S. V0 IN is the input pin of power supply to generate V0 voltage for LCD. V0 S is the input pin of power supply to sense the V0 voltage. V0 OUT V0 IN & V0 S should be connected together by FPC. 8 VDD Power supply. 9 VSS Ground. 10 VDD Power supply. 11 NC No connection. 12 /CS 13 IF3 14 IF1 LCD bias Vg Vm Note 1/N bias (2/N) x V0 (1/N) x V0 N= 5 to 12 Chip select input pins. Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D7 become high impedance. Parallel / Serial data input select input IF3 IF1 MPU interface type H L 80 series 8-bit parallel H L 68 series 8-bit parallel

8 PAGE 8 OF 16 Table 2(b): Pin assignment Pin No. Symbol Description 15 /RST Reset input pin. When RST is L, initialization is executed. E_RD pin is only used in parallel interface. MPU Type E_RD Description Enable clock pin: Write status: The data on D0 to D7 are latched at 16 E_RD 6800-series E the falling edge of the E signal. Read status: The data on D0 to D7 are latched at the rising edge of the E signal. Read enable clock input pin 8080-series /RD The data on D0 to D7 are latched at the falling edge of the /RD signal. 17 VDD Power supply. 18 D7 19 D6 20 D5 21 D4 22 D3 Data pins. 23 D2 24 D1 25 D0 RW_WR pin is only used in parallel interface. 26 RW_WR MPU Type 6800-series 8080-series 27 A0 Register select input pin. In parallel interface. A0= H : D0 to D7 is display data. A0= L : D0 to D7 is control command. 28 NC No connection. 29 NC No connection. RW_WR Description Read / Write control input pin. RW Write status: RW = L. Read status: RW = H. Write enable clock input pin /WR The data on D0 to D7 are latched at the rising edge of the /WR signal.

9 PAGE 9 OF Absolute Maximum Ratings 4.1 Electrical Maximum Ratings for IC Only Table 3 Parameter Symbol Min. Max. Unit Supply Voltage (2) VDD V Supply Voltage (2) VDD2,VDD3,VDD4,VDD V Supply Voltage (3) VLCD (V0-XV0) V Input voltage range Vin -0.3 VDD+0.5 V Note: 1. The modules may be destroyed if they are used beyond the absolute maximum ratings. 2. Voltages are all based on VSS = 0V. 3. Voltage relationship: V0. Vg. Vm. VSS. XV0 must always be satisfied. 4.2 Environmental Conditions Item Operating temperature (Topr) Table 4 Storage temperature (Tstg) (Note 1) Remark Min. Max. Min. Max. Ambient temperature (Ta) -20 C +70 C -30 C +80 C Dry Humidity (Note 1) 90% max. RH for Ta 40 C No condensation < 50% RH for 40 C < Ta Maximum operating temperature Vibration (IEC ) cells must be mounted on a suitable connector Shock (IEC ) Half-sine pulse shape Frequency: Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. Pulse duration: 11 ms Peak acceleration: 981 m/s 2 = 100g Number of shocks: 3 shocks in 3 mutually perpendicular axes. 3 directions 3 directions Note 1: Product cannot sustain at extreme storage conditions for long time.

10 PAGE 10 OF Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = 25 C, VDD = 2.8V, VSS=0V. Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit Supply voltage (logic) VDD-VSS V Supply voltage (LCD) VLCD At Ta = -20 C, VDD=2.8V, Note 1 - TBD - V At Ta =25 C, VDD=2.8V,Note 1 - ~ V At Ta =70 C, VDD=2.8V, Note 1 - TBD - V Input signal voltage V IH H level 0.7VDD - VDD V V IL L level VSS - 0.3VDD V Supply Current IDD - TBD - ma (Logic & LCD) Supply voltage of white LED backlight Luminance (on the backlight surface) VLED Forward current =20mA Number of LED dies = V cd/m 2 Note 1: There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. 5.2 Timing Characteristics Reset Timing At Ta =-20 C To +70 C, VDD = 2.8V, VSS=0V. Table 6

11 PAGE 11 OF 16 Notes: 1. Spike due to an electrostatic discharge on RST line does not cause irregular system reset according to the table below: 2. During the Resetting period, the display will be blanked (The display is entering blanking sequence, which maximum time is 120 ms, when Reset Starts in Sleep Out mode. The display remains the blank state in Sleep In mode.) and then return to Default condition for Hardware Reset. 3. Spike Rejection also applies during a valid reset pulse as shown below: 4. When Reset applied during Sleep In Mode. 5. When Reset applied during Sleep Out Mode. 6. It is necessary to wait 5msec after releasing RST before sending commands. Also Sleep Out command cannot be sent for 120msec.

12 PAGE 12 OF System Bus Read / Write Characteristics (8080-series MPU) At Ta =-20 C To +70 C, VDD = 2.8V, VSS=0V. Table 7 Note 1: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr+tf) (tcyc8-tcclw-tcchw) for (tr +tf) (tcyc8-tcclr-tcchr) are specified. Note 2: All timing is specified using 20% and 80% of VDD as the reference. Note 3: tcclw and tcclr are specified as the overlap between /CS being L and WR and RD being at the L level. Figure 3: Parallel Interface Characteristics bus (8080-series MCU)

13 PAGE 13 OF System Bus Read / Write Characteristics (6800-series MPU) At Ta =-20 C To +70 C, VDD = 2.8V, VSS=0V. Table 8 Note 1: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr+tf) (tcyc6-tewlw-tewhw) for (tr+tf) (tcyc6-tewlr-tewhr) are specified. Note 2: All timing is specified using 20% and 80% of VDD as the reference. Note 3: tewlw and tewlr are specified as the overlap between /CS being L and E. Figure 4: Parallel Interface Characteristics bus (6800-series MCU)

14 PAGE 14 OF Power ON/OFF sequence (TBD) 5.4 Power Flow Chart For Different Power Modes (TBD) 6. Electrical & Optical Characteristics (TBD) 7. CSTN Panel Inspection Specifications

15 PAGE 15 OF 16

16 PAGE 16 OF Remark Varitronix Limited reserves the right to change this specification. Tel: (852) FAX: (852) URL: - END -

VL-PS-COG-C144MVGI-08 REV.A (COG-C144MVGI-08) DEC/2009 PAGE 2 OF 26 DOCUMENT REVISION HISTORY DATE DESCRIPTION CHANGED BY DOCUMENT REVISION

VL-PS-COG-C144MVGI-08 REV.A (COG-C144MVGI-08) DEC/2009 PAGE 2 OF 26 DOCUMENT REVISION HISTORY DATE DESCRIPTION CHANGED BY DOCUMENT REVISION PAGE 2 OF 26 DOCUMENT REVISION HISTORY DOCUMENT REVISION DATE DESCRIPTION CHANGED BY CHECKED BY FROM TO A 2009.12.09 First Release. BETTY MAO CALM ZHONG PAGE 3 OF 26 CONTENTS Page No. 1. GENERAL DESCRIPTION