Optimizing Your Memory Sub-System

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1 Optimizing Your Memory Sub-System AKA Choosing the right memories Design with Freescale Toronto Jim Cooke Ecosystems Enablement Les Marentette FAE Manager November 6, Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron s production data sheet specifications. Information, products, and/or specifications are subject to change without notice. All information is provided on an AS IS basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 1

2 November 8,

3 November 8,

4 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program November 8,

5 NVM architectures NOR Each memory cell can be accessed independent of the others Physical "contact" to each memory location NAND Memory cells are grouped in stacks called strings Physical contacts to the cells are limited Why NOR 5+ year life cycle D Direct to read circuitry Fewer litho transitions G Direct to read circuitry Broad portfolio S D D Good read performance G G S execute In Place capable True random access G S D G D S "bitline" Easier to design Lowest cost at 128Mb and below Assumed higher quality G S D S May 14 th 5

6 Single Level Cell vs. Multi-Level Cell SLC 1 physical bit = 1 data bit Cell either programmed or erased Higher performance SLC NAND more reliable than MLC NAND MLC 1 physical bit = 2 data bits 3 bit per cell technology out for NAND Cells partially programmed Lower performance Higher density and lower cost per MB May 14 th 6

7 NOR product attributes Simple command sets Cost effective at low densities Stable architectures Value added features (XiP, security, quality, small data, etc) Serial Low pin counts Easy PCB routing Smallest footprint Synchronous operations Cheapest low density Parallel Basic add/data interface Asynchronous random access Synchronous burst operations Higher throughput Best XiP architecture 7

8 NAND product attributes Low pin counts Cheapest cost/bit at high densities Frequent conversions/migrations required Fast programming Discrete Some controllers support boot Some standards (ONFI) Common packages Needs SW for error management Demand paging saves bits Managed Error management onboard Some controllers support boot Higher density reach Easier conversions/migrations Standards (MMC, USB, usd ) 8

9 NAND technology challenges How to manage the ECC requirements? NAND controllers with high ECC capability ECC NAND managed solutions on-die ECC Fully managed solutions emmc, eusb, others How to manage lower Endurance? Understand the application and usage model How does the file system work? How often are you programming? How big is the data file/s? What is the PLC of your system? Determines PE Cycles and Density Required Intersecting your project and the memory technology is key to success! November 13 9

10 NAND system solutions for Industry Raw NAND for application expert with NAND data Host Controller I management and ready to support ECC needs. NAND Interface FTL ECC LLD NAND BUS Raw NAND ECC NAND for application that do not want to change the ECC with the NAND litho shrink. Host Controller II NAND Interface FTL LLD NAND BUS ECC NAND ECC Serial NAND for application requiring high density with Serial protocol. Host Controller III SPI Interface FTL LLD SPI BUS SPI ECC emmc interface for application that want to offload by any Host Controller IV emmc NAND NAND data management with a standard interface. emmc Interface LLD MMC BUS ECC FTL eusb interface for application that want to offload by any Host Controller V eusb NAND NAND data management with a standard interface. eusb Interface LLD USB BUS ECC FTL LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling November 13 10

11 Level of Management by NAND solutions Level of Management by NAND Solution Raw NAND ECC NAND (On-Die ECC) Fully Managed (emmc, eusb, SSD) Complexity of Customer Development (NAND Management by Host) New Product Qualification (Complexity & Effort) Higher Med Low Higher Med Low Relative Cost Low Med Higher Trade offs between Complexity, Qualification Effort & Cost 11

12 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program November 8,

13 DRAM product attributes Many different types Fast read performance Fast writes Leading edge requires many conversions Discrete Common standards Common packages Many levels in a single system Module Higher density reach Easier conversions/migrations Standards and custom options ECC management enabled 2010 Micron Technology, Inc. 13

14 DRAM Selection Criteria Which DRAM technology(ies) are supported or planned by the controller Proto/Production timeframe & expected life support needs? What type of controller (based on Intel/ARM/MIPS/etc)? How many gigabytes are needed by the app? What is the memory bus width? How much bandwidth (MB/sec) is needed by the app? Are there any preferred packages (discrete or module)? Does the customer require upgrade/cost reduction path (higher density/litho transition)? 2010 Micron Technology, Inc. 14

15 PC Speed Trend Typical 1yr Speed Cadence Interrupted High End V V V V V V Main Stream -800/ V V V/1.35V V -1600/ V/1.20V -1600/ V/1.20V Value Technology DDR2/DDR3 DDR3 DDR3 DDR3/DDR4 DDR3/DDR4 DDR3/DDR4 Use PC trend to find price sweet spot DDR4 enables the performance and power step 2010 Micron Technology, Inc. 15

16 Product Comparison Density Prefetch Size Core Voltage-Vdd I/O Voltage Max Clock Freq. Burst Lengths Configurations PASR Output Driver DPD LPDDR1 LPDDR2- S2/S4 DDR1 DDR2 DDR3 Up to 8Gb Up to 8Gb Up to 1Gb Up to 2Gb Up to 4Gb 2n 2n/4n 2n 4n 8n V/1.35V 2.5V 1.8V 1.55V 1.5V 1.35V (DDR3L) 1.8V, 1.2V 1.2V Same as VDD Same as VDD Same as VDD 200Mhz 200/533MHz 200MHz 533MHz 1066MHz 2, 4, 8, 16 4, 8, 16 2, 4, 8 4, 8 BC4, 8 x16, x32 x16, x32 x4, x8, x16 x4, x8, x16 x4, x8, x16 Yes Yes No No No LVCMOS_18 HSUL_12 SSTL_2 SSTL_18 SSTL_15 Yes Yes No No No 2010 Micron Technology, Inc. 16

17 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program November 8,

18 Density Needs for Boot Memory Low Density Mid Density High Density 0.5Mb 128Mb 1 Gb 2 Gb 4 Gb 8 Gb 2GB 16 GB 64GB SPI NOR 0.5Mb to 1Gb Parallel NOR 32Mb to 2Gb SLC NAND Small Page 128Mb to 512mb Low Density SLC 1Gb to 4Gb High Density SLC 8Gb to 64Gb MLC NAND 16Gb to 256 Gb Managed NAND emmc 4GB to 64GB eusb 2GB to 16 GB Q

19 Solutions for different requirements NOR vs. NAND Lowest Floor Cost ($) Lowest $/GB Serial NOR Parallel NOR SLC NAND Managed NAND MLC NAND Longer lifecycles Ease of use Diverse products Lower Floor cost Code, Code+Data Shorter lifecycles Focus on cost/gb Expanding markets Mostly Data Focused Customer Requirements Dictate the Solution 19

20 Performances consideration for system solutions Host Controller I Raw NAND NAND Interface FTL ECC LLD NAND BUS Host Controller II NAND Interface FTL LLD NAND BUS On-Die ECC NAND ECC Host Controller III emmc emmc Interface LLD emmc BUS ECC FTL Device Throughput Raw NAND, ECC NAND and emmc require different management software The correct performance evaluation is at system LLD = Low Level Driver ECC = Error Correction Code FTL = NAND Scheduling Logical Mapping, Bad Block Management, Wear Leveling November 13 20

21 Flash Architectures Component Level All architectures have their advantages Trend in the industry moving toward the lower pin count architectures 21

22 Performance Comparison Small Data May 14 th Micron Confidential 22

23 Performance Comparison Large Data May 14 th Micron Confidential 23

24 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program November 8,

25 November 8,

26 Micron Product Longevity Program (PLP) Micron s PLP addresses customer needs to: Protect their design investments by ensuring a minimum of 10 years of availability on mainstream memory devices Provide stability to existing designs by offering a 2-year conversion timeline in the event of a part-number change (e.g. die shrink) Micron s full product portfolio supported via normal roadmaps: No change to standard products PLP products are a subset of the Micron portfolio Micron s customers now have a choice: Buy standard products with existing service and support OR Buy PLP products to obtain increased longevity and stability November 8,

27 Micron s Product Longevity Program Automotive Industrial Multi-Market Micron is focused on markets requiring long lifecycles: Automotive, industrial, medical Micron s PLP benefits: 10-year longevity from PLP introduction date 2-year conversion timeline: 1-year LTB (last-time buy) + 1-year LTS (last-time ship) from PTN (product-termination notification) date November 8,

28 Micron Has a Proven Track Record Micron has a history of supporting memory products for long periods of time and we intend to continue this with PLP! November 8,

29 November 8,

30 Line Card PLP products are High-volume runners Purchased by large numbers of customers Suitable for automotive, industrial, medical, and other applications requiring 10-year longevity PLP Line Card is a subset of the entire Micron portfolio Not all product families and densities are represented November 8,

31 Optimizing Your Memory Sub-System Non-Volatile Memory Choices DRAM Technologies Trade-offs to consider for System Design Performance Boot Time Power Density Schedule / Time to Market / Sweet spot Product life targets Summary - Product Longevity Program November 8,

32 What s next? Customers 1. Understand memory usage 2. Understand true cost 3. Work with a trustworthy supplier Suppliers 1. Provides technology leadership & product longevity 2. Architecture transparency 3. Systems expertise & silicon/solution standards 32

33 Broadest Portfolio Industry s broadest portfolio Computing, server/networking, embedded, mobile, consumer Manufacturing Expertise/Stability Automotive Storage Graphics / Consumer Networks Server Wireless Personal Computing Industrial 33

34 Micron s Product Portfolio NOR Parallel and Serial NOR product portfolios, densities 512Kb-2Gb+ Technology leadership on 65nm and 45nm. Automotive and industrial qualified solutions NAND Discrete and managed solutions, densities 128Mb-64GB Technology leadership on 20nm Automotive and industrial qualified e MMC solutions Legacy support for low density NAND 34

35 DRAM Micron s Product Portfolio Legacy SDRAM through cost/performance leading DDR3 offerings Discrete and module DRAM solutions High speed RLDDRx Options Automotive and industrial qualified solutions 35

36 Working with industry leaders Architecture alignment Industry standards Reference designs Co-marketing Board support package Schematic reviews Third-party enablement Debug services Software solutions Strategic initiatives Micron is your trusted advisor 36

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