Product Specifications

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1 Product Specificatio L75S655BGAS. General Information 5MB 6Mx7 SDRAM PC ECC REGISTERED PIN SODIMM Description: The L75S655B is a 6Mx 7 Synchronous Dynamic RAM high deity memory module. This memory module coists of eighteen CMOS Mx8 bits withbanks Synchronous DRAMs in TSOPII mil packages, two bit Registered buffers in TSOP package, a zero delay buffer PLL in TSOP package, a and a K EEPROM in 8pin TSSOP package. This module is a pin smalloutline dual inline memory module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each SDRAM. Features: Registered 8 byte SDRAM pin SODIMM High Speed MHz CL Burst Mode Operation Auto & Self refresh Capability (89 Cycles/6ms) LTTL compatible inputs and outputs Single. ±. power supply // Addressing (Row/Column/Bank) MRS cycle with address key programs EPROM Serial Presence Detect PCB height: (mil), double sided component Gold (Au) contacts Leadfree/RoHS complaint Pin AA BA, BA Name CB~CB7 CLK CKE, CKE CS#, CS# RAS# CAS# WE# Function Address inputs Bank Select Address Data /Outpu t Check bits Clock Inpu t Clock Enable Inpu t Chip Select Inpu t Row Address Strobe Column Address Inpu t Write Enable 7 Data input/output mask DD Power Supply (.) SS Ground * REF Power Supply for Referenc e Order Information: L 75S655BGA S X SDA SCL NC Serial Data /Outpu t SPD Clock Inpu t No Connect * These pi are not used in this module. DRAM DIE (Option) DRAM MANUFACTURER S SAMSUNG MODULE SPEED GA: CL L: Leadfree/RoHS irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE OF 8

2 Product Specificatio L75S655BGAS. Pin Configuration Pin Front Number Side SS DD SS 5 7 DD 9 A A A 5 SS 7 DQ8 9 DQ9 5 DD SS 57 CB 59 CB 6 CLK 6 DD 65 RAS# 67 WE# 69 CS# 7 CS# Pin Back Number Side SS DD SS DD A A A5 6 SS 8 6 DD SS 58 CB 6 CB5 6 CKE 6 DD 66 CAS# 68 CKE 7 A 7 NC Pin Front Number Side 7 CS#* 75 SS 77 CB 79 CB 8 DD SS 9 95` DD A6 5 A8 7 SS 9 A9 A/AP DD SS DD SS SDA DD Pin Back Number Side 7 CS#* 76 SS 78 CB6 8 CB7 8 DD SS DD A7 6 BA 8 SS BA A DD SS DD 6 8 SS SCL DD * These pi are not used in this module irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE OF 8

3 Product Specificatio L75S655BGAS. Functional Block Diagram RCS# RCS# R R U U U5 U R R5 DQ8 DQ9 5 U U R6 U6 U5 CB CB CB CB CB CB5 CB6 CB7 R U U R7 U7 U R U U U8 U7 Κ DD CS# CS# 7 BA BA A A RAS# CAS# CKE CKE WE# U REGISTERS LE CK U RCS# RCS# R R7 RBA RBA RA RA RRAS# RCAS# RCKE RCKE RWE# CLK DQn SCL CK ~ CK8 CK9 A Ohm Serial PD A Ohm A PLL CLOCK DRIER. p F SDA * delay from input to output of PLL. SDRAMs for each CK Registers Every DQpin of SDRAM CK ~ CK9 PLL_CLK DD ss Two.uF Capacitors per SDRAM To all SDRAMs irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE OF 8

4 Product Specificatio L75S655BGAS. Absolute Maximum Ratings alue oltage on any pin relative to ss oltage on DD s upply relative to ss N I, OUT. ~. 6 DD, DDQ. ~. 6 Storage temperature TSTG 55 ~ +5 C Power dissipation PD 8 W Short circuit current IOS 5 Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Recommended DC Operating Conditio ( TA = C to +7 C) Min Typ Max Note Supply voltage DD, DDQ... 6 high voltage low voltage high voltage low voltage leakage current (s) H I.. DDQ+. L I.. 8 OH. IOH = OL. IOL = IL I 8 8 ua Notes:. I H (max) = 5.6 AC. The overshoot voltage duration is <=.. I L (min) =. AC. The undershoot voltage duration is <=.. Any input <= IN < = DDQ. Capacitance ( TA = 5 C, f = MHz, D D =.) Min Max capacitance (A ~ A, BA ~ BA) CIN 5 capacitance (RAS#, CAS#, WE#) CIN 5 capacitance (CKE, CKE) CIN 5 capacitance (CLK) CIN capacitance (CS#, CS#) CIN5 capacitance ( ~ 7) CIN6 Data input/output capacitance ( ~ ), (CB ~ CB7) COUT irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE OF 8

5 Product Specificatio L75S655BGAS. DC Characteristics ( Recommended operation condition unless otherwise noted, TA = C to +7 C) Test Condion ersion GA Note Operating current (One bank active) C Burst length = trc > = tr C(min) IOL = 5 Precharge standby current powerdown mode in CP CKE <= IL( max), tcc = 9 CPS CKE & CLK <= I L( max), tcc = Precharge standby current non powerdown mode in CN CNS CKE >= IH ( min), >= IH ( min), tcc = signals are changed one time during CKE >= IH( min), CLK <= I L( max), tcc = oo signals are stable 7 85 Active standby current in power down mode CP CKE <= IL( max), tcc = 6 CPS CKE & CLK <= I L( max), tcc = Active standby current powerdown mode (One bank active) in non CN CNS CKE >= IH( min), >= IH(min), tcc = signals are changed one time during CKE >= IH( min), CLK <= I L ( max), tcc = signals are stable 8 55 Operating current (Burst mode) C IOL = Page burst Banks actived tccd = CLKs 65 Refresh current C5 Self refresh current C6 trc > = tr C( min) 5 CKE <=. 5 Note:. Measured with outputs open..refresh period is 6ms. irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE 5 OF 8

6 Product Specificatio L75S655BGAS. AC Operating Test Conditio ( DD =., TA = C to +7 C) alue AC input levels (IH/ I L)./. timing measurement reference level. rise and fall time tr/tf = / timing measurement reference level. load condition See Fig.. tt!=!. 5 OH (DC)!=!.,!IOH!=! OL!(DC)!=!.,!IOL!=! Z!=! (Fig.!)!DC!output!load!circuit! (Fig.!)!AC!output!load!circuit! Operating AC ersion GA Note Row active to row active delay tr RD( min) 5 RAS# to CAS# delay tr CD( min) Row precharge time Row active time Row cycle time tr P( min) tr AS( min) 5 tr AS( max) us tr C( min) 65 Last data in to row precharge tr DL( min) CLK Last data in to Active delay td AL( min) CLK +trp Last data in to new col. addrees delay tc DL( min) CLK Last data in to burst stop tb DL( min) CLK Col. address to col. address delay tc CD( min) CLK Number of valid output data CAS Latency = CLK Notes:. The minimum number of clock cycles is determined and then rounding off to the next higher integer.. Minimum delay is required to complete write.. All parts allow every cycle column address change.. In case of row precharge interrupt, auto precharge and by dividing the minimum time required with clock cycle time read burst stop. irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE 6 OF 8

7 Product Specificatio L75S655BGAS. Operating AC Min GA Max Note CLK cycle time CAS latency = tcc CAS latency = 7.5 CLK to valid output delay CAS latency = tsac CAS latency = 5., data hold time CAS latency = toh CAS latency = CLK high pulse width CLK low pulse width setup time hold time tch. 5 tcl. 5 tss. 5 tsh. 8 CLK to output in LowZ tslz CLK to output in Hiz CAS latency = tshz CAS latency = 5. Notes:. s depend on programmed CAS latency.. If clock rising time is longer than, (tr/.5) should. Assumed input rise and fall time (tr & tf) =. if tr & tf is longer than, traient timecompeation should i.e.,[(tr + tf)/] should be added to the parameter. be added to the parameter. be coidered, irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE 7 OF 8

8 Product Specificatio L75S655BGAS. Package Dimeio.66 (67.56).5 (6.6) s : Inches (Millimeters).6 ±.9 (. ±.). (6.) (.). (5.8 ) R.78 Min (. Min). (.).5 (.7).9 (.).9 (.8) (.6).8 (.). (.5) Z Y.7 (.8).5 Max (.8 Max).57 Min (. Min). ±.9 (. ±.) Tolerance: +.6 (.5) unless otherwise specified Revision History: Detail Z.6 ±.9 (.5 ±.).6 ±.9 (. ±.). Min (.5 Min).9 ±. (. ±.5).8 ±.6 (. ±.5).5 (.7) Detail Y D ate Rev. Page Changes 9 //. All Update datasheet irtium Technology, Inc. 5 Tomas, Rancho Santa Margarita, CA 9688 PAGE 8 OF 8

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