Scientific Computing with Intel Xeon Phi Coprocessors
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1 Scientific Computing with Intel Xeon Phi Coprocessors Andrey Vladimirov Colfax International HPC Advisory Council Stanford Conference 2015 Compututing with Xeon Phi Welcome Colfax International, 2014
2 Contents 1 MIC Architecture, Developer s Perspective 2 Case Studies Astrophysics (offload story) N-body simulation (offload vs native in a cluster) Finanical Monte Carlo (heterogeneous clustering) Computational fluid dynamics (legacy code) 3 Colfax Developer Training Compututing with Xeon Phi Welcome Colfax International, 2014
3 1. MIC Architecture from Developer s Perspective Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
4 Intel Xeon Phi Coprocessors and the MIC Architecture PCIe end-point device High Power efficiency 1 TFLOP/s in DP Heterogeneous clustering For highly parallel applications which reach the scaling limits on Intel Xeon processors Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
5 Examples of Solutions with the Intel MIC Architecture Colfax s CXP7450 workstation with two Intel Xeon Phi coprocessors xeonphi.com/workstations Colfax s CXP9000 server with eight Intel Xeon Phi coprocessors xeonphi.com/servers Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
6 Intel Xeon Phi Coprocessors and the MIC Architecture 18 cores/socket 3 GHz 57 to 61 cores at 1 GHz 2-way hyper-threading 4 hardware threads per core Up to 768 GB of DDR3 RAM 6 16 GB cached GDDR5 RAM 256-bit AVX vectors 512-bit IMCI vectors C/C++/Fortran; OpenMP/MPI Linux OS (on host and on coprocessor) Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
7 Linux µos on Intel Xeon Phi coprocessors (part of MPSS) lspci grep -i "co-processor" 06:00.0 Co-processor: Intel Corporation Xeon Phi coprocessor 3120 series (rev 20) 82:00.0 Co-processor: Intel Corporation Xeon Phi coprocessor 3120 series (rev 20) sudo service mpss status mpss is running cat /etc/hosts grep mic host-mic0 mic host-mic1 mic1 ssh mic0 cat /proc/cpuinfo grep proc tail -n 3 processor : 237 processor : 238 processor : 239 user@mic0% ls / amplxe dev home lib64 oldroot proc sbin sys usr bin etc lib linuxrc opt root sep3.10 tmp var Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
8 Offload and Native modes Explicit offload mode: Native mode: Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
9 Optimization Areas Common methods for Intel Xeon CPUs and Intel Xeon Phi coprocessors: 1 Scalar optimization (compiler-friendly practices) 2 Vectorization (must use 16- or 8-wide vectors) 3 Multi-threading (must scale to 100+ threads) 4 Memory access (streaming access or tiling) 5 Communication (offload, MPI traffic control) Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
10 Getting Ready for the Future Knights Landing (KNL) next generation of Intel MIC architecture 3x the performance of current generation Available as a stand-alone processor or as a coprocessor Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
11 Getting Ready for the Future The best way to prepare applications for KNL is to optimize them for Intel Xeon Phi coprocessors based on KNC. Compututing with Xeon Phi MIC Architecture from Developer s Perspective Colfax International, 2014
12 2. Case Studies Compututing with Xeon Phi Case Studies Colfax International, 2014
13 Astrophysical Code HEATCODE: an Offload Story xeonphi.com/papers/heatcode Compututing with Xeon Phi Case Studies Colfax International, 2014
14 Astrophysical Code HEATCODE: an Offload Story xeonphi.com/papers/heatcode Compututing with Xeon Phi Case Studies Colfax International, 2014
15 N-body Simulation: Offload vs Native in a Cluster xeonphi.com/papers/nbody-basic Compututing with Xeon Phi Case Studies Colfax International, 2014
16 N-body Simulation: Offload vs Native in a Cluster Single Precision GFLOP/s Initial N-Body Simulation Performance Processor: Intel Xeon E v2 Coprocessor: Intel Xeon Phi 7120P Multithreaded Vectorized with SoA Scalar Tuning xeonphi.com/papers/sc Tiled, Unrolled Compututing with Xeon Phi Case Studies Colfax International, 2014
17 N-body Simulation: Offload vs Native in a Cluster Performance, TFLOP/s Intel Xeon E v2 CPUs (4 nodes) Intel Xeon Phi 7120P coprocesors (4 per node) N=2 20 particles (strong scaling) 3 Xeon Phi/node 1 Xeon Phi/node 2 Xeon Phi/node CPU Xeon Phi, native MPI Xeon Phi, MPI+Offload Number of Nodes or Coprocessors (P) xeonphi.com/papers/sc14 4 Xeon Phi/node 92% eff 76% eff Compututing with Xeon Phi Case Studies Colfax International, 2014
18 Asian Option Pricing: Heterogeneous Clustering xeonphi.com/papers/heterogeneous Compututing with Xeon Phi Case Studies Colfax International, 2014
19 Computational Fluid Dynamics: Legacy Code xeonphi.com/papers/shallow Compututing with Xeon Phi Case Studies Colfax International, 2014
20 3. Colfax Developer Training Compututing with Xeon Phi Colfax Developer Training Colfax International, 2014
21 Colfax Developer Training Intel Xeon Phi Coprocessor Programming Future-Proofing Applications for Knights Landing (KNL) xeonphi.com/training Compututing with Xeon Phi Colfax Developer Training Colfax International, 2014
22 Free Training for HPCAC Stanford 2015 Participants xeonphi.com/hpcac2015 Compututing with Xeon Phi Colfax Developer Training Colfax International, 2014
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