ESD8451, SZESD8451. ESD Protection Diodes. Low Capacitance ESD Protection Diode for High Speed Data Line
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1 ESD51, SZESD51 ESD Protection Diodes Low Capacitance ESD Protection Diode for High Speed Data Line The ESD51 Series ESD protection diodes are designed to protect high speed data lines from ESD. Ultra low capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. Features Low Capacitance (.3 pf Max, I/O to GND) Protection for the Following IEC Standards: IEC 1 (Level ) ISO15 33 pf / k ±3 kv Contact Low ESD Clamping Voltage SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q11 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications USB 3. MHL. esata X3DFN CASE 15AF XDFN CASE 711AM P, A = Specific Device Code M = Date Code PIN CONFIGURATION AND SCHEMATIC 1 MARKING DIAGRAMS PIN 1 P M A M MAXIMUM RATINGS (T J = 5 C unless otherwise noted) Rating Symbol Value Unit Operating Junction Temperature Range T J 55 to +15 C Storage Temperature Range T stg 55 to +15 C = Lead Solder Temperature Maximum (1 Seconds) T L C IEC 1 Contact (ESD) IEC 1 Air (ESD) ESD ESD ±15 ±15 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. kv kv ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. See Application Note AND3/D for further description of survivability specs. Semiconductor Components Industries, LLC, 1 June, 1 Rev. 1 Publication Order Number: ESD51/D
2 ESD51, SZESD51 ELECTRICAL CHARACTERISTICS (T A = 5 C unless otherwise noted) Symbol V RWM I R V BR I T V HOLD I HOLD R DYN I PP V C Parameter Working Peak Voltage Maximum Reverse Leakage V RWM Breakdown I T Test Current Holding Reverse Voltage Holding Reverse Current Dynamic Resistance Maximum Peak Pulse Current Clamping I PP V C = V HOLD + (I PP * R DYN ) V BR V C V RWM V HOLD R DYN I PP I HOLD I T I R I I R I T I HOLD I PP V C = V HOLD + (I PP * R DYN ) R DYN V HOLD V RWM V C V BR V ELECTRICAL CHARACTERISTICS (T A = 5 C unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage V RWM I/O Pin to GND 3.3 V Breakdown Voltage V BR I T = 1 ma, I/O Pin to GND V Reverse Leakage Current I R V RWM = 3.3 V, I/O Pin to GND 5 na Reverse Holding Voltage V HOLD I/O Pin to GND.5 V Holding Reverse Current I HOLD I/O Pin to GND 17 ma Clamping Voltage (Note 1) V C IEC1, ± KV Contact V ESD51MUT5G Clamping Voltage ESD51NT5G Clamping Voltage V C I PP = 3.7 A, / s pulse 13.7 V V C I PP = 5. A, / s pulse 17. V ESD51MUT5G Clamping Voltage TLP (Note ) ESD51NT5G Clamping Voltage TLP (Note ) V C I PP = A IEC 1 Level equivalent (± kv Contact, ± kv Air) I PP = 1 A IEC 1 Level equivalent (± kv Contact, ± kv Air) V C I PP = A IEC 1 Level equivalent (± kv Contact, ± kv Air) I PP = 1 A IEC 1 Level equivalent (± kv Contact, ± kv Air) 11. V V 1. ESD51MUT5G Dynamic Resistance R DYN Pin1 to Pin Pin to Pin ESD51NT5G Dynamic Resistance R DYN Pin1 to Pin Pin to Pin1.. Junction Capacitance C J V R = V, f = 1 MHz..3 pf Junction Capacitance C J V R = V, f =.5 GHz.19.5 pf 1. For test procedure see Figure 1 and application note AND37/D.. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 5, t p = 1 ns, t r = ns, averaging window; t 1 = 3 ns to t = ns.
3 ESD51, SZESD51 TYPICAL CHARACTERISTICS Figure 1. ESD51N ESD Clamping Voltage Screenshot Negative kv Contact per IEC1 Figure. ESD51N ESD Clamping Voltage Screenshot Positive kv Contact per IEC1 Figure 3. ESD51MU ESD Clamping Voltage Screenshot Negative kv Contact per IEC1 Figure. ESD51MU ESD Clamping Voltage Screenshot Positive kv Contact per IEC1 3
4 ESD51, SZESD51 TYPICAL CHARACTERISTICS C (pf) V BIAS (V) Figure 5. ESD51MUT5G CV Characteristics C (pf) V BIAS (V) Figure. ESD51NT5G CV Characteristics m1 m m1 m (db) (db) E7 1E 1E9 1E1 3E1 1 1E7 1E 1E9 1E1 3E1 FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. ESD51MUT5G S1 Insertion Loss Figure. ESD51NT5G S1 Insertion Loss CAPACITANCE (pf) FREQUENCY (GHz) Figure 9. ESD51MUT5G Capacitance over Frequency CAPACITANCE (pf) FREQUENCY (GHz) Figure 1. ESD51NT5G Capacitance over Frequency
5 ESD51, SZESD51 TYPICAL CHARACTERISTICS TLP CURRENT (A) TLP CURRENT (A) V C, VOLTAGE (V) Figure 11. ESD51MUT5G Positive TLP I V Curve Figure 13. ESD51MUT5G Negative TLP I V Curve V C, VOLTAGE (V) V IEC, EQUIVALENT (kv) 1 V IEC, EQUIVALENT (kv) TLP CURRENT (A) TLP CURRENT (A) V C, VOLTAGE (V) Figure 1. ESD51NT5G Positive TLP I V Curve V C, VOLTAGE (V) Figure 1. ESD51NT5G Negative TLP I V Curve V IEC, EQUIVALENT (kv) 1 V IEC, EQUIVALENT (kv) 5
6 ESD51, SZESD51 Latch Up Considerations ON Semiconductor s series of ESD protection devices utilize a snap back, SCR type structure. By using this technology, the potential for a latch up condition was taken into account by performing load line analyses of common high speed serial interfaces. Example load lines for latch up free applications and applications with the potential for latch up are shown below with a generic IV characteristic of a snapback, SCR type structured device overlaid on each. In the latch up free load line case, the IV characteristic of the snapback protection device intersects the load line in one unique point (V OP, I OP ). This is the only stable operating point of the circuit and the system is therefore latch up free. In the non latch up free load line case, the IV characteristic of the snapback protection device intersects the load line in two points (V OPA, I OPA ) and (V OPB, I OPB ). Therefore in this case, the potential for latch up exists if the system settles at (V OPB, I OPB ) after a transient. Because of this, ESD51 should not be used for HDMI applications ESD1 or ESD have been designed to be acceptable for HDMI applications without latch up. Please refer to Application Note AND911/D for a more in depth explanation of latch up considerations using ESD series devices. ESD51 Latch up free: USB. LS/FS, USB. HS, USB 3. SS, DisplayPort ESD51 Potential Latch up: HDMI 1./1.3a TMDS Figure 15. Example Load Lines for Latch up Free Applications and Applications with the Potential for Latch up Table 1. SUMMARY OF SCR REQUIREMENTS FOR LATCH UP FREE APPLICATIONS Application VBR (min) (V) IH (min) (ma) VH (min) (V) ON Semiconductor ESD Series Recommended PN HDMI 1./1.3a TMDS ESD1, ESD USB. LS/FS ESD, ESD51 USB. HS. N/A 1. ESD, ESD51 USB 3. SS. N/A 1. ESD, ESD, ESD51 DisplayPort ESD, ESD, ESD51
7 ESD51, SZESD51 IEC 1 Spec. Level Test Voltage (kv) First Peak Current (A) Current at 3 ns (A) Current at ns (A) IEC1 Waveform I peak 1% 9% 3 ns ns 1% t P =.7 ns to 1 ns Figure 1. IEC1 Spec Transmission Line Pulse (TLP) Measurement Transmission Line Pulse (TLP) provides current versus voltage (I V) curves in which each data point is obtained from a 1 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 17. TLP I V curves of ESD protection devices accurately demonstrate the product s ESD capability because the 1s of amps current levels and under 1 ns time scale match those of an ESD event. This is illustrated in Figure 1 where an kv IEC 1 current waveform is compared with TLP current pulses at A and 1 A. A TLP I V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. 5 Coax Cable L 1 M V C S Attenuator V M Oscilloscope DUT Figure 17. Simplified Schematic of a Typical TLP System I M 5 Coax Cable Figure 1. Comparison Between kv IEC 1 and A and 1 A TLP Waveforms 7
8 ESD51, SZESD51 ORDERING INFORMATION ESD51NT5G, SZESD51NT5G* Device Package Shipping XDFN (Pb Free) / Tape & Reel ESD51MUT5G X3DFN (Pb Free) 1 / Tape & Reel SZESD51MUT5G* X3DFN (Pb Free) 15 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD11/D. *SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q11 Qualified and PPAP Capable.
9 ESD51, SZESD51 PACKAGE DIMENSIONS X3DFN,.x.3,.355P, (1) CASE 15AF ISSUE A X PIN 1 INDICATOR (OPTIONAL).5 C.5 C D TOP VIEW A1 SIDE VIEW A B A E C SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M, CONTROLLING DIMENSION: MILLIMETERS. MILLIMETERS DIM MIN MAX A.5.33 A1.5 b.. D.5. E..3 e.355 BSC L.17.3 RECOMMENDED MOUNTING FOOTPRINT*.7 X.3 e X b 1 X L.5 M C A B.5 M C A B BOTTOM VIEW X.31 1 DIMENSIONS: MILLIMETERS See Application Note AND39/D for more mounting details *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 9
10 ESD51, SZESD51 PACKAGE DIMENSIONS XDFN 1.x.,.5P (SOD ) CASE 711AM ISSUE O PIN 1 INDICATOR.1 C.1 C.1 C D ÉÉ e/ TOP VIEW A1 SIDE VIEW 1 e NOTE 3 BOTTOM VIEW A B E b A.5 C C SEATING PLANE.5 M C A B X L.5 M C A B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y1.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. MILLIMETERS DIM MIN MAX A.3. A1.5 b.3.53 D 1. BSC E. BSC e.5 BSC L..3 RECOMMENDED SOLDER FOOTPRINT* X.7 PIN 1 1. X. DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. HDMI is a registered trademark of HDMI Licensing, LLC. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor s product/patent coverage may be accessed at /site/pdf/patent Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. Typical parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor 1951 E. 3nd Pkwy, Aurora, Colorado 11 USA Phone: or 3 3 Toll Free USA/Canada Fax: or 3 37 Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: 955 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative ESD51/D
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More informationIs Now Part of To learn more about ON Semiconductor, please visit our website at
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