CD4023BC Buffered Triple 3-Input NAND Gate

Transcription

1 CD4023BC Buffered Triple 3-Input NAND Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P- channel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to DD and SS. Ordering Code: Features October 1987 Revised August 2000 Wide supply voltage range: 3.0 to 15 High noise immunity: 0.45 DD (typ) Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS parametric ratings Symmetrical output characteristics Maximum input leakage 1 µa at 15 over full temperature range Order Number Package Number Package Description CD4023BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow CD4023BCS M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4023BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X tot he ordering code. CD4023BC Buffered Triple 3-Input NAND Gate Connection Diagram Block Diagram 1 / 3 Device Shown Top iew *All Inputs Protected by Standard CMOS Input Protection Circuit Fairchild Semiconductor Corporation DS

2 CD4023BC Absolute Maximum Ratings(Note 1) (Note 2) DC Supply oltage ( DD ) 0.5 DC to +18 DC Input oltage ( IN ) 0.5 DC to DD +0.5 DC Storage Temp. Range (T S ) 65 C to +150 C Power Dissipation (P D ) Dual-In-Line 700 mw Small Outline 500 mw Lead Temperature (T L ) (Soldering, 10 seconds) 260 C Recommended Operating Conditions DC Supply oltage ( DD ) Input oltage ( IN ) Operating Temperature Range (T A ) 5 DC to 15 DC 0 DC to DD DC 40 C to +85 C Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device operation. Note 2: SS = 0 unless otherwise specified. DC Electrical Characteristics (Note 3) Symbol Parameter Conditions 40 C +25 C +85 C Min Typ Min Typ Max Min Max I DD Quiescent Device Current DD = DD = DD = OL LOW Level Output oltage DD = DD = DD = OH HIGH Level Output oltage DD = DD = DD = IL LOW Level Input oltage DD =5, O = DD =10, O =9.0 I O <1µA DD =15, O = IH HIGH Level Input oltage DD =5, O = DD =10, O =1.0 I O <1µA DD =15, O = I OL LOW Level Output Current DD =5, O = (Note 4) DD = 10, O = DD = 15, O = I OH HIGH Level Output Current DD = 5, O = (Note 4) DD = 10, O = DD = 15, O = I IN Input Current DD = 15, IN = DD = 15, IN = Note 3: SS = 0 unless otherwise specified. Note 4: I OH and I OL are tested one output at a time. Units µa ma ma µa 2

3 AC Electrical Characteristics (Note 5) T A = 25 C, C L = 50 pf, R L = 200k, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units t PHL Propagation Delay, HIGH-to-LOW Level DD = DD = ns DD = t PLH Propagation Delay, LOW-to-HIGH Level DD = DD = ns DD = t THL, Transition Time DD = t TLH DD = ns DD = C IN Average Input Capacitance Any Input pf C PD Power Dissipation Capacity (Note 6) Any Gate 17 pf Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: C PD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note AN-90. CD4023BC 3

4 CD4023BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, Narrow Package Number M14A 4

5 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) CD4023BC 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5

6 CD4023BC Buffered Triple 3-Input NAND Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.