isppac-powr1208p1 Evaluation Board PAC-POWR1208P1-EV

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1 March 2007 Introduction Application Note AN6059 The Lattice Semiconductor isppac -POWR1208P1 In-System-Programmable Analog Circuit allows designers to implement both the analog and digital functions of a power supply monitoring and sequencing subsystem within a single integrated circuit. By integrating analog functions such as comparators and programmable slew rate FET drivers with the digital functionality of a Programmable Logic Device (PLD), the isppac-powr1208p1 provides the power-supply designer with a rich set of features in a single device. ISP (In-System-Programmability) provides the designer with an unprecedented level of flexibility, allowing him to configure analog parameters such as threshold voltages as well as defining state machines and combinatorial logic functions. All configuration data is stored internally in E 2 CMOS nonvolatile memory. Programming a configuration is accomplished through an industry-standard JTAG IEEE interface. Evaluation Board The evaluation board (Figure 1) allows the designer to quickly configure and evaluate the isppac-powr1208p1 on a fully assembled printed-circuit board. The double-sided board supports a 44-pin TQFP package, a header for user I/O, a JTAG programming cable connector, and an uncommitted pad array for user prototyping. JTAG programming signals can be generated by using an ispdownload programming cable connected between the evaluation board and a PC s parallel (printer) port. Both analog and digital features of the isppac-powr1208p1 can be easily configured using PAC-Designer software. Figure 1. Evaluation Board 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 1 an6059_01.1

2 A complete schematic for the evaluation board is shown in Figure 2. Figure 2. Schematic INP CLK INP R1B POWER INP C5 4.7U C1 0.1U 26 CLK J INP C3 0.1U R1D R1E R1F R1G R10 R9 J9 R8 INP R7 R2 10K 10 J7.1 J7.2 J7.3 J7.4 INP P1 P5 POR VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VMON11 VMON12 IN1 IN2 IN3 IN4 TDI TMS TCK SW1 Reset C4 0.1U 25 POR 32 VMON1 33 VMON2 34 VMON3 35 VMON4 36 VMON5 37 VMON6 38 VMON7 40 VMON8 41 VMON9 42 VMON10 43 VMON11 44 VMON12 6 IN1 7 IN2 8 IN3 9 IN4 isppac-powr1208p1 TDI TCK TMS S CH HVOUT1 4 HVOUT2 3 HVOUT3 2 HVOUT4 1 COMP1 23 COMP1 COMP2 COMP2 22 COMP3 COMP3 21 COMP4 COMP4 20 COMP5 COMP5 19 COMP6 COMP7 17 COMP7 COMP8 16 COMP CREF R3 R4 C2 1U R5 R6 J8 R1C HVOUT1 HVOUT2 HVOUT3 HVOUT4 TDI TMS TCK P5 P2 Programming Interface Lattice Semiconductor s ispdownload cable can be used to program the isppac-powr1208p1 on the evaluation board. This cable plugs into a PC-compatible s parallel port connector, and includes active buffer circuitry inside its DB-25 connector housing. The other end of the ispdownload cable terminates in an 8-pin pitch header connector which plugs directly into a mating connector provided on the evaluation board. Prototype Area A 19x18 grid (0.100 pitch) of uncommitted, plated through holes with annular-ring pads is provided as a user prototyping area. Adjacent to this uncommitted array are two 19-hole rows providing easy connections to both power and ground. This prototyping area allows the user to build small circuits directly on the evaluation board. In the case of larger circuits, the evaluation board can be readily connected into off-board circuitry through P5, into which can be mounted a 20 x 2 header. Power Supply Considerations The isppac-powr1208p1 operates with power supplies ranging from 2.7V to 5.5V, and allows for separate core () and I/O (INP) voltages. Voltages ranging from 0 to 5.94V may be monitored at any of the 12 VMONx 2

3 pins independent of the values of and INP. For device programming, however, must be set between 3.0 and 5.5V. On the evaluation board, and INP are normally connected together with a user-removable jumper (J7.5). This jumper can be removed to allow for independent and INP supplies. Input/Output Connections Connectors are provided for key functions and test points on this evaluation board, as shown In Figure 3. Power is supplied through two color coded (RED = +, BLACK = -) banana jacks in the upper right corner of the board. The JTAG programming cable is connected to a keyed header (P1) in the lower right corner of the board. A PCB land pattern is provided for the addition of an additional JTAG interface header (P2) to allow for connecting multiple evaluation boards into a multi-device programming chain. Access to the isppac-powr1208p1 s I/O pins is available at P5, which is a 2x20 row of pads to which one may attach test probes or a ribbon-cable connector. At this point all of the device s I/O pins (except those required for the JTAG programming interface) are accessible. Figure 3. I/O and Jumpers J9 OUT[5-8] INP J8 HVOUT[1-4] INP HVOUT PULL-UP J INP P5 VMON1 VMON3 VMON5 VMON7 VMON9 VMON11 HVOUT4 HVOUT2 IN2 IN4 INP COMP8 COMP6 COMP4 COMP2 POR VMON2 VMON4 VMON6 VMON8 VMON10 VMON12 HVOUT3 HVOUT1 IN1 IN3 COMP7 COMP5 COMP3 COMP1 CLK isppac- POWR1208P1 Power P1 JTAG Interface 1 Jumper Options Several jumpers are provided on the evaluation board to make it simple to implement common circuit configurations. These jumpers are: J7 - positions 1-4 connect pull-up resistors to the high voltage outputs HVOUT1-4, and allow the user to enable the pull-ups on an output-by-output basis. The pull-up voltage is selected by J8. Position 5 (the rightmost position) is used to connect INP to, and should normally be left in place. This jumpers needs to be removed when using separate and INP supplies. J8 - Selects a pull-up voltage to which the High-Voltage outputs (HVOUT1-4) may be pulled up to, either or INP. 3

4 J9 - Selects whether open-drain digital outputs - are pulled up to (upper position), INP (lower position), or not pulled up at all. These outputs are pulled up through 2KΩ resistors. Controls and Indicators A reset switch is provided on the evaluation board which pulls the input pin low when it is depressed, re-initializing the isppac-powr1208p1. s are also provided as an aid to debugging. One shows whether the board has power applied, while another is connected to the JTAG line, and will flash when a download is being performed. Additionally, four s are attached to the isppac-powr1208p1 s - lines. By adding appropriate code to the sequencer program, these s can be made to indicate the internal status of the isppac-powr1208p1, and can be a useful debug aid. PCB Artwork Figure 4. Silk Screen 4

5 Figure 5. Top-side Foil Figure 6. Bottom-side Foil 5

6 Component List Quantity Ref. Designators Description 2 C1, C3 0.1µF capacitor 1 C2 1µF capacitor 1 C4 0.1µF capacitor 1 C5 4.7µF capacitor 1 J7 2 x 5 header strip, dual row, 0.1 spacing 2 J8,J9 1 x 3 header strip, single row, 0.1 spacing 5 _A, _B, _C, _D, T-1-3/4 red POWER_ 1 P1 1x8 header strip, single row, 0.1 spacing 1 P3 Red banana jack 1 P4 Black banana jack 1 R1 ohm SIP-8 resnet, 7-resistor SIP, bussed type 1 R2 10K resistor 8 R3, R4, R5, R6, R7, R8, R9, R10 2K 5% resistor 1 SW3 Pushbutton switch 1 _ T1-3/4 green 1 U1 isppac-powr1208p1 Ordering Information Description isppacpowr1208 Precision Evaluation Board isppac Power Manager 1208 Precision Design System Ordering Part Number PACPOWR1208P1-EV PAC-SYSPOWR1208P1 China RoHS Environment-Friendly Use Period (EFUP) 10 Technical Support Assistance Hotline: LATTICE (North America) (Outside North America) isppacs@latticesemi.com Internet: Revision History Date Version Change Summary February Previous Lattice releases. March Added Ordering Information section. 6