A Mixed Flash Translation Layer Structure for SLC-MLC Combined Flash Memory System

Transcription

1 A Mixed Flash Translation Layer Structure for SLC-MLC Combined Flash Memory System Seung-Ho Park, Jung-Wook Park, Jong-Min Jeong, Jung-Hwan Kim, Shin-Dug Kim Department of Computer Science, Yonsei University, Republic of Korea Corporate Technology Operations, Samsung Electronics Co., Republic of Korea {shpark, pjppp, Abstract NAND flash memory is a nonvolatile storage that is often used for its advantages of small size, non-mechanical, shock resistance, and low power consumption. With the recent drop in its price, NAND flash memory is on the verge of taking place of hard disk drive. Depending on the number of bits stored in a single cell, flash memory can be divided into SLC (single-level cell) NAND and MLC (multi-level cell) NAND. The SLC NAND has faster transfer speed and higher cell endurance than MLC NAND flash memory. The only disadvantage of SLC is its manufacturing cost per megabyte. In this paper, we propose the SLC-MLC mixed flash translation layer with 3-slot block mapping method for block level address translation and block relocation algorithm. The simulation result shows high writing performance, performing 9 percent SLC speed even though 7 percent of the proposed design consists of MLC NAND.. Introduction With nonvolatile, shock resisting and low power consuming characteristics, NAND flash memories are used widely as storage devices for various embedded systems such as digital cameras, MP3 players, and portable storage devices. Furthermore, a flash based SSD (solid state disk) begins to take place of traditional magnetic hard disk drive in the computer systems because of rapid increase in its storage space per cost. Flash memory and hard disk are similar in that they are both nonvolatile storages; however, requested accesses to the flash memory can be performed much faster than conventional hard disks, because it does not require any mechanical movement. In spite of these advantages, the flash memory has also address re-mapping overhead. A NAND flash memory is composed of fixed number of blocks and each block consists of also fixed number of pages which are the basic unit of read and write operation in NAND flash memory. In contrast to other storage devices, flash memory does not allow its own pages to be overwritten without erasing it. To modify a page, whole block including the requested page must be erased in order to perform the write operation. Since write operation and erase operation are relatively slower than read operation, this erase-before-write limitation lowers the performance of flash memory. Therefore, page allocation mechanism should be able to utilize more space for data modification to reduce additional erase and write operations. FTL (flash translation layer) is an intermediate software module that exists between the host and a flash memory [][]. The main function of FTL is creation of the mapping table, which remaps a write operation to an empty page beforehand; this reinforces erase-before-write limitation of the flash memory [3]. So far, various FTL algorithms have been proposed to improve overall performance of the flash memory based storage systems. The recent drop in price of flash memory made storage volume to increase per unit price, greatly extending its employed areas. Furthermore, MLC (multi level cell) NAND flash memory is enabling the cost lower. With relatively superior performance, long life time, and stability, SLC (single level cell) NAND flash memory is more expensive than MLC NAND flash memory. In this paper, we propose the low-priced and high-performance SLC-MLC mixed flash memory system. This system is composed of relatively small amount of SLC NAND flash memory space and a larger amount of MLC NAND flash memory space; the proposed MFTL (mixed flash translation layer) effectively manages these two kinds of flash memories. The results show that 9% of the performance can be achieved through the proposed structure compared to the only SLC NAND flash memory based structure, although 7% of storage is composed of MLC NAND flash memory. The rest of this paper is organized as follows: Section presents the background of flash translation layer and the characteristics of current SLC and MLC NAND flash. Sections 3 shows the SLC-MLC mixed flash translation layer and its architecture. In Section 4, the performance and the analysis of this system are provided. Finally, we conclude at Section 5.. Background A NAND flash memory is composed of a fixed number of blocks, and each block is made up of several pages. In turn, each page is composed of a data area and its associated spare area. In current NAND flash memory named large block NAND flash memory, each block consists of 64 or 8 pages depending on the chip architecture, and each page is composed of 48 bytes of data area and 64 bytes of a spare area [4]. There is a limitation to the writing operation on the large block NAND flash memory. Similar to a stack structure, when a page is needed to be written

2 to a specific block, it has to be written from the first empty page to the last empty page of the block. For instance, a data cannot be written on the third page from the bottom in a block unless the first and second pages are already full with other data. A page is a basic unit of read/write operation in NAND flash memory. Generally, user data resides in data area and other metadata, such as management information and error correction code (ECC) are located in the spare area in order to manage the mapping information and handle bit errors from reading or writing the page [5]. Made of multiple pages, block is the unit of erase operation one of the three basic operations which include read, write, and erase operation. This means that erase operation can only be performed in a much larger unit than read or write operation. When a part of free space in flash memory is written, the written pages are no longer available unless they are erased. In order to prevent these erase-before-write overheads, rising from deletion of the block carrying a needed page and re-copying of valid pages within the block, out-of-place update method is adopted. The latest copy of data is considered valid, and the old data that has been overwritten by a new data is considered invalid. As the usage period of flash memory lengthens and the number of updates increases, the amount of invalid pages within the system also increases. When free space within a flash memory goes below a certain limit or a number of invalid pages increase too much, the system requires a process which reclaims invalid pages into free pages; this is called garbage collection or reclamation. To sum up, there is the restriction of operation mismatch between a host, which generates read and write operations, and inside the NAND flash memory, which causes read, write and erase operations. In order to address these limitations, the FTL scheme is adopted... Flash translation layer (FTL) Overwriting on a previously written page is not possible in flash memory. Therefore, in order to perform the write operation on a certain page, the block including the page must be erased. However, this process re-writes not only the targeted page but also other valid pages within the block, raising the cost of the update process. In order to minimize the overhead, mapping table is used to place the data in an already empty page; this is one of the main roles of flash translation layer (FTL) [6]. FTLs can be classified into two types, page-mapped (or fine-grained) and block-mapped (or coarse-grained), based on the applied mapping technique. In the block-mapped FTL design, a logical sector generated from the host is divided into a logical block address (LBA) and a logical page address (LPA). A logical block address can be derived by dividing the sector address by the number of pages within a single block, and a logical page address becomes the offset (or the remainder) within the block. Then, by using block mapping table, logical block address is converted into physical block address (PBA). The size of block mapping table is only proportional to the number of physical blocks in a NAND flash memory. However, this block mapping scheme cannot be used on large block NAND flash memory. That is because as mentioned in Section, data must be written from the first page and then in numerical order. In a page-mapped FTL scheme, a logical sector can be mapped anywhere within a NAND flash memory. Therefore, storage management is far more flexible than the block mapping technique. However, address translation needs to be processed by each page, requiring the size of page mapping table to be proportional to the total number of pages in a NAND flash memory. Therefore, the amount of RAM required by a pagemapped FTL scheme is significantly greater than block-mapped FTL scheme. In order to complement disadvantages in page-mapped FTL and block-mapped FTL scheme, combination of two schemes, hybrid mapping, is often used. In this method, a physical block address is extracted from a logical block address using block mapping table, and then within the selected physical block, position of the page is determined by inner page mapping table. One of the mapping schemes is a technique based on the concept of a replacement block [7]. This technique allocates a replacement block when an overwriting comes to an existing page in a block. However, the page in the replacement block has to be located to the same block offset. Moreover, the replacement block itself can have its own replacement blocks as form of a linked list replacement blocks. When a logical block is merged, a data block, which includes original pages, and all replacement blocks should be erased, even though they have several free pages. Another mapping scheme, a log block technique is suggested to utilize the block for update [8][9]. When an overwriting occurs, this technique reduces the number of merge operations by locating the data to temporary block, called log block. In contrast to the replacement block, the page can be placed to log block in out-of-place manner which utilizes the space of update block and delays the merge operations... SLC/MLC NAND flash memory NAND flash memory chips can be categorized into two types: SLC (single-level cell) and MLC (multi-level cell). One of the main differences is that SLC NAND stores two binary states, either a binary or a binary, in a single cell; on the other hand, MLC NAND can store in four states, -,,, or. In other words, SLC can hold one bit while MLC can hold two. Even though MLC NAND can store more bits in each cell, its durability is lower than SLC NAND. When a given block in NAND flash memory goes through a certain number of erasewrite cycles, the block wears out and read/write process turns unstable, becoming a bad block. Typically, durability of SLC NAND is, erase cycles and that of MLC NAND is, erase cycles as shown in the Table []. Table. Differences between SLC and MLC devices Features MLC NAND SLC NAND Bits per cell Page size,-4,34 bytes, bytes Pages per block Endurance <, <, Read operation 5 us 5 us Write operation 6-9 us -3 us Erase operation 3 ms.5- ms

3 Also, there are differences in operation speeds. Generally, the write operation in a NAND flash memory requires a relatively long latency compared to the read operation. As shown in Table, erase operation, which must be performed on a whole block, takes greater processing time than read/write operations, which are based on a single page unit. The SLC NAND shows better performance than the MLC NAND. In contrast, the MLC NAND represents lower cost than the SLC NAND. Therefore a management, that can handle advantages of SLC NAND and MLC NAND, is required, which shows high performance and low cost. 3. Mixed flash translation layer (M-FTL) In this section, the proposed design and implementation of FTL for SLC-MLC mixed flash memory architecture are described in detail. This system is composed of a small amount of SLC NAND flash and a relatively large amount of MLC NAND flash memory in order to lower the price. 3.. Address mapping The basic idea of mixed flash translation layer is the joint management of the high performance SLC NAND flash memory and the low price MLC NAND flash memory. In order to achieve this goal, entire-physical block address (E-PBA) is created in the middle by joining physical block address of SLC NAND and physical address of MLC NAND. E-PBA simply puts these physical block address spaces in order. Given that SLC and MLC physical address spaces are n and m from respectively, the address space of E-PBA becomes (m+n+) from. In such cases, upper addresses of E-PBA point to the PBA of SLC NAND, and rest of the addresses point to the PBA of MLC NAND. We can get the physical MLC block address space by subtracting the total number of SLC physical blocks from E-PBA. The physical SLC block address simply equals the E-PBA. For example, let us assume that there are 8 physical blocks in the SLC NAND and 6 physical blocks in the MLC NAND as depicted in Figure. Numbers of E-PBA address space and physical block address of SLC NAND matches as they are both from to 7; E-PBA address space from 8 to 3 equals MLC NAND physical block addresses from to 5. For address translation, the proposed design initially goes through a block address mapping table and finally reaches desired physical sector by using inner block page mapping table. Especially, this paper focuses on the block level address translation method using 3-slotted block address mapping table. Each entry of this table is divided into three slots, and E-PBA number can be stored in each slot. Therefore, a single logical block address can be mapped into three different E-PBAs. Each slot is called,, and, starting from the bottom. A logical block whose is occupied by a SLC NAND space of E-PBA is called SLC-mode, and likewise, a logical block whose is taken by MLC NAND space of E-PBA is called MLC-mode. Both MLC NAND address and SLC NAND address can be saved in ; however, only SLC NAND address can be saved in and. In case of the example in Figure, and can only be E-PBA numbers of to 7. Figure. Entire-physical address space (E-PBA) The amount of logical page address space that can be stored in a single logical block address depends on the kinds of flash memory product that is being used. In a typical block-mapped FTL scheme, the number of pages in a physical block matches the address range of single logical block; however, since SLC NAND and MLC NAND flashes are mixed, the two of those physical blocks can be different. In this case, the larger block becomes the standard. Usually the size of MLC physical block equals or is larger than the size of SLC physical block. In this paper, we assume that a SLC NAND physical block is made up of 64 pages, and a MLC physical block is composed of 8 pages. In this scenario, 8 pages can be mapped on a single logical block address, becoming the standard. But, the size of a page has to be same in order to match the units of read operation and write operation; we use the page size of 48 bytes except the spare area. HOST Logical block address (LBA) SLC-mode SLC-mode MLC-mode MLC-mode Entire-physical block address (E-PBA) Figure. 3-slot block mapping table SLC address space MLC address space When a logical block address is in MLC-mode, other two slots except cold slot, ( and ) become extra-slots since the address space of a logical block equals to the number of pages in the MLC NAND block. These extra slots are used as log buffers when overwriting occurs in of the logical block address; the system assigns extra-slot as a new block for new data

4 writing. In contrast, when a logical block address is in SLC-mode, only remains as extra slot because the size of SLC NAND block is only half of that of MLC NAND block. In both cases, since extra slots are allocated only in SLC NAND addresses, overwriting only occurs in SLC NAND block, guaranteeing fast write speed. 3.. Writing algorithm Similar to a stack structure, when a data is added to a specific block in a large-block NAND flash memory, the data must be written from the first empty page of the block [4]. In this paper, since we are using the large-block NAND flash memory, we are following the above mechanism. When overwrite request is made in a specific logical block, write operation is performed sequentially from the topmost empty page which is closest to hotslot s physical page. On the contrary, when the new write request, which is not overwriting, is made, the operation is performed sequentially from the bottommost empty page which is closest to s physical address of page. Figure 3 shows before and after situation of write sequences performed on a specific logical block address. In this case, we assume that a SLC NAND block is composed of four physical pages and a MLC NAND block consists of eight physical pages. Also, it is supposed that the logical block address has been already occupied by six valid pages, whose logical page addresses are,, 3, 4, 5 and 6, respectively, in each SLC-mode and MLC-mode. The upper-left portion of Figure 3 illustrates the sequence of writes from the host along with target logical page addresses. Note that each extra-slot appears in a reversed way starting from topmost as the physical page address. In Figure 3, (a) and (b) shows each case of SLC-mode and MLC-mode. Firstly, the switch merge is the simplest merge operation that has little overhead cost. It changes only a few values of 3-slot block mapping table without any reading or writing operations on the flash memory. The switch merge only occurs when the logical block address is in SLC-mode and all the pages in a physical SLC block on either or are overwritten once. Mode-switch merge can be performed in a straightforward manner as well. This merge operation can be executed when the logical block address is in MLC-mode and all pages in the physical MLC block in are invalidated, which changes MLC-mode to SLC-mode. The partial merge occurs on situation that all pages are valid in one of SLC blocks in SLC-mode. Finally, the normal merge is the most expensive merge operation since it has to collect all valid pages scattered in three of the blocks. : empty slot : valid page : invalid page (a) Switch merge (b) Mode-switch merge write sequence write() write() 3 write(7) 4 write() 5 write() allocate a new block valid valid 5 valid valid valid 5 valid (c) Partial merge (d) Normal merge Figure 4. Possible merge operations 3.3. Block Relocation valid valid (a) SLC-mode 45 invalid 3 valid 7 invalid invalid valid valid (b) MLC-mode Figure 3. Write requests on each mode 45 invalid 3 valid 7 invalid invalid When three physical blocks associated with a logical block are filled with pages, they must be reclaimed in order to remove invalid pages. This process is called merge operation. There are four types of merge operations that can be performed in this M- FTL system as illustrated in the Figure 4: switch, mode-switch, partial, and normal merge. The M-FTL assigns SLC blocks as the extra-slots in order to give high writing performance. However, after repeating the writing process for a certain period of time, all SLC blocks will be exhausted and finally, no more additional writing operations can be achieved. It is efficient to make frequently updated blocks be stored in SLC NAND and to make cold blocks stay in MLC NAND because of the SLC NAND characteristics. Here, the block relocation algorithm is offered to utilize the MLC NAND. The block relocation algorithm plays two major roles. One is reclaiming blocks with invalid pages to create empty blocks. The other role is moving cold pages from SLC NAND blocks to MLC NAND blocks. These two kinds of jobs are performed simultaneously by scanning the 3-slot block mapping table in a circular manner. In other words, the scanning process comes to the first entry of the block mapping table when it reaches to the end. Firstly, the block relocation algorithm checks an entry whether the logical block is in SLC-mode or in MLC-mode since there is only one extra-slot in case of SLC-mode and there are two extra slots in case of MLC-mode. It skips the merging operation on the

5 logical block unless any extra-slot exists. After performing this relocation process on the certain number of logical blocks, reclaiming SLC NAND blocks, it stops the scanning and saves the location which points to the current logical block address. When it continues the block relocation, it begins with the logical block address pointer that has been saved before. The block relocation requires a flag so-called candidate-bit to save current state of the logical block in order to distinguish its coldness. In the scanning process, it verifies the candidate bit on condition that no extra-slot is allocated in SLC-mode, which means the data in the logical block are static. When the candidate-bit has been set previously, all the pages in that logical block are forcibly moved to a MLC NAND block, which can cause mode switching, SLC-mode to MLC-mode. The opposite direction of mode switching was discussed in Section 3.. However, when the candidate-bit has not been set before, it postpones the chance of mode switching by setting the candidatebit. Otherwise, in scanning process, the candidate-bit becomes unset state when the logical block has extra-slot allocated. All these processes are shown in Figure 5. This block relocation sequence should be triggered when the number of free blocks decreases below the predefined limit and when the device is in idle time to avoid the copy overhead. number of write requests on each logical block appears to be similar to the Figure 6(b). This indicates that frequently updated area utilizes the SLC NAND blocks. In contrast to the SLC, the number of writing operations on MLC displays almost flat line since static data tend not to move in and out inside the MLC NAND block. Note that each x-axis represents logical address, not physical address. (a) Write requests on LBAs check next LBA (b) Write operations on SLC forced merge clear candidate bit YES extra-block? NO candidate bit set candidate bit mode switch (c) Write operations on MLC Figure 5. Block relocation algorithm 4. Experimental evaluation A NAND flash memory simulator is developed to evaluate overall performance of the storage system which includes both SLC and MLC NAND flash memories. The storage is composed of 3Gbytes of SLC NAND and 7Gbytes of MLC NAND. The simulator operates M-FTL algorithm based on disk I/O traces extracted from general PC usage. The trace data are gathered from Gbytes hard disk drive with Windows NTFS file system. There are 499,36 requests in this trace; 66,798 read requests and 3,564 write requests. The trace includes several common works during a day windows updates, installing applications, downloading files, playing games, using disk management utility, compress and decompress of files, and usage of several applications. 4.. Hot and cold data separation Hot/cold data separation plays an important role in management flash memory system []. Figure 6 shows that hot/cold data block separation can be achieved by M-FTL. The Figure 6. SLC/MLC data separation 4.. Writing performance Table shows the performance of each device and storage systems with various configurations. Two log block based FTL techniques are compared with the proposed M-FTL. The M-FTL shows almost 9% of writing speed compared to SLC log block scheme with 8,49 Kbytes/s which is composed of only SLC NAND. Although the M-FTL has slightly more overheads on merging as shown in Table 3, the concentration of writing operations on SLC NAND physical block successively improves the overall performance of writing. Also, it shows low device cost since it is composed of 8Gbytes of MLC NAND and 3Gbytes of SLC. As a reference, the ratio of merging operation on each case is represented in Table 3. Note that the merge write of the M-FTL does not show any value since the merge operation always changes MLC-mode to SLC-mode but not in the reverse way. Also, there are more extra overheads on SLC log block technique than MLC due to the smaller SLC physical block. Each device speed in Table can be obtained by subtracting the percentage of each merging overhead from the chip speed.

6 Table. Performance of each device Device measurement read write chip speed MLC log block SLC log block SLC MLC M-FTL MLC chip (Kbytes/s) 4, 3,333 SLC chip (Kbytes/s) 8,, operations on MLC(%) operations on SLC (%) speed (Kbytes/s) 8,87,986 operations on MLC (%) operations on SLC (%) speed (Kbytes/s) 54,876 8,856 operations on MLC (%) 48 5 operations on SLC (%) 5 95 speed (Kbytes/s) 45,548 8,49 Table 3. Overhead of merging ratio read while merging write while merging MLC log block 7.96 %.43 % SLC log block 3.4 %.44 % M-FTL SLC % 6.7 % MLC.7 %. % 4.3. Reasonable SLC NAND size Appropriate size of SLC NAND flash memory is presented in Figure 7. The additional trace is used in this experiment in order to examine the amount of proper SLC size of the proposed architecture. Larger size of trace extracted from one day PC usage is repeatedly simulated to generate bulk of data traffics per day. The x-axis represents the number of days passed. Generally, as time goes by, the available space of SLC declines slowly. However, when the capacity of SLC cannot stand the frequent writing operations generated from host, no more free space is available even though the block relocation performs. Figure 7 shows that the M-FTL stays in a steady state with 3Gbytes of SLC NAND flash memory capacity although days has passed. (a) Using Gbytes of SLC NAND (b) Using Gbytes of SLC NAND (c) Using 3Gbytes of SLC NAND 5. Conclusion In this paper, we have proposed M-FTL mechanism that can utilize both SLC NAND flash memory and MLC NAND flash memory. Its performance advantage mainly comes from the concentration of writing operations to the SLC NAND which operates faster than the MLC NAND, especially in writing. Through the suggested methods such as 3-slot block mapping table, writing algorithm and block relocation technique, M-FTL could be lower the price of storage significantly by using small space of SLC NAND memory. It can separate frequently updated hot data and static cold data to SLC NAND and MLC NAND, respectively and it shows 9 percent of writing performance compared to SLC only based architecture although it is composed of MLC NAND mostly. For future research, the page mapping table management could be examined in order to achieve fast access to the desired page with this proposed architecture. Also, a method of improving performance of read/write operations via parallelization of flash chips is to be explored. Acknowledgement This work was supported by Samsung Co. Next-Generation Mobile Platform based on SSD and PP for the Ubiquitous Computing Environment project. 6. References [] T.S. Chung, D.J. Park, S.W. Park, D.H. Lee, S.W. Lee and H.J. Song System Software for Flash Memory: A Survey, EUC 6, LNCS 496, pp , 6. [] S.H. Lim and K.H. Park, An Efficient NAND Flash File System for Flash Memory Storage, IEEE Transactions on Computers, Vol. 55, No. 7, July 6. [3] S.W. Lee, D.J. Park, T.S. Chung, D.H. Lee, S.W. Park and H.J. Song, A Log Buffer-Based Flash Translation Layer Using Fully-Associative Sector Translation, ACM Transactions on Embedded Computing System, Vol. 6, No. 3, Article 8, 7. [4] NAND Flash technical paper, SLC-Large block 8G bit, Gx8, K9K8G8UA, Available from: 7. [5] E. Harari, R. D. Norman, and S. Mehrota, Flash eeprom system, United States Patent, no. 5,6,987, February 997. [6] E. Gal and S. Toledo, Algorithms and Data Structures for Flash Memories, ACM Computing Surveys, Vol. 37, No., pp , June 5. [7] A. Ban, Flash file system, United States Patent, no. 5,44,485, April 995. [8] J. Kim, J.M. Kim, S.H. Noh, S.L. Min and Y. Cho, A Space- Efficient Flash Translation Layer for Compactflash Systems, IEEE Transactions on Consumer Electronics, Vol. 48, No., May. [9] S.Y. Kim and S.I. Jung, A Log-based Flash Translation Layer for Large NAND flash memory, Advanced Communication Technology, Vol. 3, pp , February 6. [] J. Cooke, Flash Memory Technology Direction, WinHEC, May, 7. [] J.W. Hsieh and T.W. Kuo, Efficient Identification of Hot Data for Flash Memory Storage Systems, ACM Transactions on Storage, Vol., No., pp. -4, February 6. Figure 7. SLC size and usability