COSC Operating Systems Design, Fall 2001, Byunggu Yu. Chapter 9 Memory Management (Lecture Note #8) 1. Background

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1 COSC Operating Systems Design, Fall 2001, Byunggu Yu Chapter 9 Memory Management (Lecture Note #8) 1. Background The computer programs, together with the data they access, must be in main memory (at least partially) during execution: 1.1 Typical instruction execution cycle (1)fetch instruction > decode (2)fetch operands (depending on the instruction) (3)execute the instruction on the operands (4)store the results in memory 1.2Address Binding Different address representations: Symbolic Address (e.g., int i and double j) Logical Address (i.e., offset) Physical Address Compile time: If it is not known where the process will reside in memory: Bind Symbolic Addresses to Logical Addresses (i.e., relocatable addresses) If it is known where the process will reside in memory (e.g.,.com of DOS): Bind Symbolic Addresses to Physical Addresses (i.e., absolute addresses) Load time: Bind Logical Addresses to Physical Addresses Execution time: If the process can move during its execution from one memory segment to another (i.e., dynamic relocation), then binding must be delayed until run time. Special H/W is required (Dynamic Binding). Bind Logical Addresses to Physical Addresses > Most modern computer systems use this dynamic address binding scheme > H/W memory management unit (MMU) is required. Example1: If it is known where the process will reside in memory (e.g.,.com of DOS) Symbolic Addresses > Physical Addresses by compiler/assembler Example2: Processes cannot move to different memory segment Symbolic Addresses > Logical Addresses by compiler/assembler

2 Logical Addresses > Physical Addresses by loader Example3: Processes can move to different memory segment (Dynamic relocation) Symbolic Addresses > Logical Addresses by compiler/assembler Logical Addresses > Physical Addresses by MMU Note that a program source code includes only symbolic addresses (e.g., int i, double j,...) MMU dynamically maps the logical address from the CPU to the physical address. 2. Simple MMU for Contiguous Memory Allocation 2.1Contiguous Memory Allocation: A process is allocated a contiguous physical memory segment. 2.2Required MMU Single Register MMU (Base register) Two Register MMU (Base and Limit registers) 2.3Multiprogramming: Dynamic Memory Allocation Strategies: First fit > fast search (***) Best fit > smallest leftover hole (**) Worst fit > largest leftover hole (*) 2.4Fragmentation Problem External Fragmentation: small memory segment > Solution #1: memory compaction > Solution #2: Paging Internal Fragmentation: memory that is internal to a partition, but is not being used. 3. Noncontiguous Memory Allocation #1 of 3: Paging Solution to the external fragmentation problem 3.1Basic Method Page size = (size of logical words (i.e., bytes))/(size of physical words (i.e., bytes))*frame size But, usually, page size = frame size and we assume this through the rest of this note. If a logical address space (i.e., a process memory address space) (or simply the entire memory) consists of 2 m bytes (words) and the page size is 2 n, then total number of pages can be as large as 2 m n (i.e., 2 m /2 n ). Furthermore, since the page size is 2 n (i.e., each page has 2 n bytes (or words)), n bits are required to address the bytes (words) in a page.

3 Therefore, the logical address is represented by: (m n) bit page number n bit page offset ==> total m bit address See Figure 9.6 to figure out how to map a logical address to a physical address dynamically by the MMU. As you can see, MMU is more complex than that of Section 2. Now, how to implement the page table in Figure 9.6 efficiently and effectively is the question (Section 3.2). Note, the internal fragmentation problem exist. Average internal fragmentation = 0.5*(page size). > small page size is desirable. > increase the size of page table by increasing the number number of pages. > How to implement the page table? 3.2Page Table Implementation Page table is an ordered list of frame numbers. Each process has its own page table and this information is stored in the Process Control Block (PCB). When the CPU switches to the next process, the page table in the PCB is loaded into the reserved page table space. Page Table Space: Solution #1: a set of registers > Problem: we need too many registers (e.g., 2 m n ). With small page size and large physical memory, this solution is impossible to implement because of the large number of registers. Entry Structure: <frame number> Solution #2: reserved memory space + 2 registers (PTBR&PTLR) > Problem: Doubles the number of memory accesses. Single memory access is mapped to two memory accesses. Too Slow! Note, PTBR stands for "Page Table Base Register" and points the first byte of the reserved memory space. PTLR stands for "Page Table Limit Register" and represents the length (i.e., the number of bytes) of the reserved memory space. Entry Structure: <frame number> Solution #3: A set of registers (TLB) + reserved memory space + PTBR&PTLR (Hybrid approach) > TLB contains the the subset of the entire page table stored in the reserved memory > While the performance depends on the hit ratio (i.e., the frame number is found in the TLB), the hit ratio is dependent on the size of TLB and the efficiency of the replacement algorithm (e.g., most recently used algorithm, LRU, LRU K,...) > See figure 9.10 in p. 294 to figure out this solution. Entry structure of the page table in the memory: <frame number> Entry structure of TLB: <page number, frame number> For protection, a couple of bits are used for each entry (see figure 9.11 in p. 296) Modified entry structure: <frame number, protection bit (or bits)> or <page number, frame number, protection bit (or bits)> Single bit example: 0 = read only, 1 = read/write 2 bit example: 00=read only, 01=execution only, 10=read/write

4 Note, each process has its own page table. Thus, the protection bit (or bits) is only for the process. 3.3Multilevel Paging Motivation: If the logical address space is very large, then the size of the page table is very large because of the larger number of pages. Problem #1: We should allocate the large page table contiguously in memory. Problem #2: Page table search time increases Problem #3: Sometimes, we want to store a portion of the entire page table in the HDD. Solution: Multilevel Paging. A logical address consists of k+1 sub addresses for k level paging. Example: 2 level Paging: Total logical address space: 2 m bytes Page size: 2 n bytes We assume that 2 e page entries can be stored in a page. Logical address structure: (m n e) bit e bit n bit 1 st (m n e) bit address points an entry in the 1 st level page table. This entry, in turn, points a page in the 2 nd level page table. 2 nd e bit address points an entry in a page of the 2 nd level page table. This entry, in turn, points a physical page (frame) in memory. Then the last n bit offset is used to find the exact physical byte (word) in memory. 3.4Inverted Page Table So far, each process has its own page table. Problem: A large amount of physical memory is consumed to store many large page tables. Solution: Inverted Page Table. There is only one global page table whose entry structure is <PID, page number> > The location of the entry in the page table is the frame number (e.g., 3 rd entry means the corresponding frame is the third frame in memory) (see Figure 9.15 in p. 301 to understand this mapping). Total number of entries in the global page table is the same as the total number of the frames in the physical memory. 3.5Shared Pages As we know, in many cases, more than two processes share some memory frames. For example, 3 rd page of process 1 and 5 th page of process 2 are mapped to the same physical frame in memory. We should note that, in contrast to regular paging, systems that use the

5 inverted paging have difficulty implementing shared memory since there is only one entry for each physical frame. That is only one process can have the access to the frame. 4. Noncontiguous Memory Allocation #2 of 3: Segmentation 4.1Basic Method: Segmentation is similar to Paging. However, unlike pages, segments have different lengths (sizes). Therefore, the segment table is a little bit different from the page table. While a page table entry has only base of the frame (physical page), a segment table entry has both the base and the limit of each segment. Limit is the length (size) of the segment. For example, is the segment consists of 10 bytes (or words), then the limit value is 10. This value is required because different segment can have different lengths. Logical address: segment number segment offset Mapping: segment base+segment offset = the address of the physical byte Note, for protection, segment offset must be smaller than the segment limit. See Figures 9.18 & 9.19 in pp to see the details. 4.2Implementation of Segment Table Same as that of page table. Register > memory with STBR&STLR > hybrid Note, STBR is Segment Table Base Register and STLR is Segment Table Limit Register. 4.3Sharing Except code segment, there is no problem in segment sharing. However, to be sharable, the shared code segment must have the same number in every process since there is branch and goto statements with logical destination addresses. Another solution: Each branch specifies the destination address as an offset from the current PC. The other Solution: There is an additional register called current segment register. Each branch destination is mapped with this register value. 4.4Re appearing external fragmentation problem Because the segment lengths are variable, external segmentation problem appears. This is the motivation of the hybrid approach. The segmentation is used only in the conceptual level and the physical level is implemented on paging scheme

6 Noncontiguous Memory Allocation #3 of 3: Segmentation with Paging (Hybrid Approach) 5.1OS/2 32 bit version with Intel See Figure 9.21 in p. 311