DS1283. Watchdog Timekeeper Chip FEATURES PIN ASSIGNMENT

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Annabelle Copeland
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1 S Watchdog Timekeeper hip FTURS Keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years; valid leap year compersation up to Watchdog timer restarts an out of control processor larm function provides notice of real time related occurrences esigned for battery operation Programmable interrupts and square wave outputs maintain pin J footprint ll registers are individually addressable via the address and data bus ccuracy is better than ± minutes/month at bytes of user nonvolatile R Optional pin SOI surface mount package Low power OS circuitry is maintained on less than µ in standby mode Optional industrial temperature range to + SRIPTION The S Watchdog Timekeeper hip is a self contained real time clock, alarm, watchdog timer, and interval timer in a pin J IP or pin SOI surface mount package. The S is specifically designed to maintain internal operations from a single low voltage supply. In fact, the only two external components required by the S are a battery and crystal. For a complete description of operating conditions, electrical characteristics, bus timing, and pin descriptions other than X, X, V T, V, RLR, INT, and INTP see the S Watchdog Timekeeper data sheet. PIN SSIGNNT INT INT X X N Q Q Q GN S PIN IP ( IL) V W INT(INT) V T RLR SQW O INTP Q Q Q Q Q V X X N Q Q Q GN W INT(INT) VT RLR SQW O INTP Q Q Q Q Q SS PIN SOI ( IL) NOT: Pin must be left disconnected. opyright by allas Semiconductor orporation. ll Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to allas Semiconductor data books. /

2 PIN SRIPTION PIN # N I/O SRIPTION INT O Interrupt Output X,X I. KHz rystal N No onnection - - I ddress Inputs: =Pin ; =Pin Q I/O ata Input/Output Q I/O ata Input/Output Q I/O ata Input/Output GN Ground Q I/O ata Input/Output Q I/O ata Input/Output Q I/O ata Input/Output Q I/O ata Input/Output Q I/O ata Input/Output I hip nable INTP O Interrupt Output P O I Output nable SQW O Square Wave Output RLR I R lear V T I attery Input INT (INT) O Interrupt Output W I Write nable V I V Input PIN SRIPTIONS X, X onnections for a standard. KHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a load capacitance ( L ) of pf. The crystal is connected directly to the X and X pins. There is no need for external capacitors or resistors. For more information on crystal selection and crystal layout considerations, please consult pplication Note, rystal onsiderations with allas Real Time locks. V T, V Inputs for batteries or power supplies between. and. volts. The V supply voltage should never exceed V T +. volts. The V T input is used to maintain all internal functions while the V input is used to keep all inputs and outputs functional. Therefore, to keep the device fully functional, V T and V must be at the same voltage potential. s long as the supply voltages are between. and. volts, the timing and the input/output levels are guaranteed. In this mode, the active current drain is m (=V IL ) and the standby current drain is. m (=V IH ). ata retention mode occurs when the V T supply is between. and. volts and the V supply is grounded. In the data retention mode the current drain is less than µ maximum at. volts (=V T. volts). The current drain specifications are stated with all outputs unloaded. RLR The RLR pin is used to clear (set to logic ) all bytes of user nonvolatile R but does not affect the registers involved with time, alarm, and watchdog functions. In order to clear the R, RLR must be forced to an input logic (. to +. volts). The RLR function is designed to be used via human interface (shorting to ground manually or by switch) and not to be driven with external buffers. This pin is internally pulled up and should be left floating when not in use. INT Interrupt on the S operates identical to interrupt on the S except that the sink and source current is limited to µ. This pin should be pulled up or down if not used. INTP Interrupt P on the S was a missing or no connection pin on the S. This interrupt works in the same manner as INT as programmed by the IPSW bit. However, INTP is also logically ORed with the S of the date register (see Figure ). This bit is called the INP bit on the S and is forced to zero on the S. When the INP bit (interrupt P bit) is set to logical one, interrupt P will be held active low. When INP is set to logical zero, INTP is always at the same logic state as INT. This pin is an open drain capable of sinking m. /

3 S WTHOG TIKPR Figure RSS IT IT RNG. SONS. SONS SONS SONS INUTS INUTS IN LR IN LR LOK, LNR, TI OF Y LR / / /P /P HR HR HOURS HR LR +/P +/P YS THIS IT IS FOR TO ZRO ON TH S INP T T Y LR OS SQW O ONTHS YRS YRS ON T IPSW IH LO PU LVL W T WF TF (RTRIGGRL/ RPTITIV OUNTOWN LR) WTHOG LR USR. SONS. SONS SONS SONS F /

4 S PIN IP PKG PIN I IN X IN. IN..... IN. IN..... IN... F IN... F G IN... K G H IN... J IN... K IN... J H /

5 S PIN SOI K G PKG PIN I IN X IN. IN. IN. IN. IN F IN. G IN S. H IN..... J IN..... K IN..... F deg. typ. J H /

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