DIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES


 Helena Stone
 3 years ago
 Views:
Transcription
1 DIGITAL CIRCUIT LOGIC UNIT 7: MULTILEVEL GATE CIRCUITS NAND AND NOR GATES 1
2 iclicker Question 13 Considering the KMap, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD 1 1 C) f = b c D) f = b d 1 1 2
3 Learning Objectives 1. Design a minimal twolevel or multilevel circuit of AND and OR gates to realize a given function. (Consider both circuits with an OR gate at the output and circuits with an AND gate at the output.) 2. Design or analyze a twolevel gate circuit using any one of the eight basic forms (ANDOR, NANDNAND, ORNAND, NOROR, ORAND, NORNOR, ANDNOR, and NANDAND). 3. Design or analyze a multilevel NANDgate or NORgate circuit. 4. Convert circuits of AND and OR gates to circuits of NAND gates or NOR gates, and conversely, by adding or deleting inversion bubbles. 5. Design a minimal twolevel, multipleoutput ANDOR, OR AND, NANDNAND, or NORNOR circuit using Karnaugh maps. 3
4 Multilevel Gate Circuits Terminology: The maximum number of gates cascaded in series between a circuit input and the output is referred to as the number of levels of gates (not to be confused with voltage levels). ANDOR circuit means a twolevel circuit composed of a level of AND gates followed by an OR gate at the output. ORAND circuit means a twolevel circuit composed of a level of OR gates followed by an AND gate at the output. ORANDOR circuit means a threelevel circuit composed of a level of OR gates followed by a level of AND gates followed by an OR gate at the output. Circuit of AND and OR gates implies no particular ordering of the gates; the output gate may be either AND or OR. 4
5 Multilevel Gate Circuits Different Realizations for the Same Expression, Z: 5
6 Multilevel Gate Circuits Example 1: 6
7 Multilevel Gate Circuits Example 1 (continued): 7
8 Multilevel Gate Circuits Example 1 (continued): 8
9 Multilevel Gate Circuits Example 1 (continued): 9
10 Multilevel Gate Circuits Example 1 (continued): 10
11 Multilevel Gate Circuits Example 1 (continued): 11
12 Multilevel Gate Circuits Example 1 (continued): 12
13 NAND and NOR Gates NAND Gates: A NAND Gate is equivalent to an AND gate followed by an inverter, or ANDNOT gate (as shown in Figure 78(b)). The ninput NAND gate s output is: 13
14 NAND and NOR Gates NOR Gates: A NOR Gate is equivalent to an OR gate followed by an inverter, or an ORNOT gate. The ninputs NOR gate s output is: 14
15 NAND and NOR Gates Functionally Complete Operations and Gates: A set of logic operations is said to be functionally complete if any Boolean function can be expressed in terms of this set of operations. If a single gate forms a functionally complete set by itself, then any switching function can be realized using only gates of that type, i.e. NAND, NOR. 15
16 NAND and NOR Gates Procedure to Determine if Functionally Complete: 1. Write out a minimum sumofproducts expression for the function realized by each gate. If no complement appears in any of these expressions, then NOT cannot be realized, and the set is not functionally complete. If a complement appears in one of the expressions, then NOT can generally be realized by an appropriate choice of inputs to the corresponding gate. (We will always assume that 0 and 1 are available as gate inputs). 16
17 NAND and NOR Gates Procedure to Determine if Functionally Complete (continued): 2. Next, attempt to realize AND or OR, keeping in mind that NOT is now available. Once AND or OR has been realized, the other one can always be realized using DeMorgan s laws if no more direct procedure is apparent. For example, if OR and NOT are available, AND can be realized by 17
18 Design of TwoLevel NAND and NOR Gate Circuits Conversion of AND and OR Gate Circuits to NAND and NOR: A twolevel circuit composed of AND and OR gates is easily converted to a circuit composed of NAND gates or NOR gates. This conversion is carried out by using F = (F ) and then applying DeMorgan s laws: 18
19 Design of TwoLevel NAND and NOR Gate Circuits Example 2: 19
20 Design of TwoLevel NAND and NOR Gate Circuits Example 2 (continued): 20
21 Design of TwoLevel NAND and NOR Gate Circuits Eight Basic Forms for TwoLevel Circuits: 21
22 Design of TwoLevel NAND and NOR Gate Circuits Eight Basic Forms for TwoLevel Circuits (continued): 22
23 iclicker Question 14 What are the output functions of the following logic gates? (50 seconds): A) NOR, NAND B) XOR, XNOR C) NAND, NOR D) [(A+B) ], [(AB) ] E) NOTOR, NOTAND 23
24 iclicker Question 14 What are the output functions of the following logic gates? (50 seconds): A) NOR, NAND B) XOR, XNOR C) NAND, NOR D) [(A+B) ], [(AB) ] E) NOTOR, NOTAND 24
25 Design of TwoLevel NAND and NOR Gate Circuits Procedure for Designing a Minimum TwoLevel NANDNAND circuit: 25
26 Design of TwoLevel NAND and NOR Gate Circuits Procedure for Designing a Minimum TwoLevel NORNOR circuit: 26
27 Design of MultiLevel NAND and NOR Gate Circuits Procedure to Design MultiLevel NANDGate Circuits: 27
28 Design of MultiLevel NAND and NOR Gate Circuits Example 3: 28
29 Circuit Conversion Using Alternative Gate Symbols Alternative Gate Symbols: Alternate symbol for inverters: The following gate symbols have been derived using DeMorgan s Laws. 29
30 Circuit Conversion Using Alternative Gate Symbols NAND Gate Circuit Conversion: 30
31 Circuit Conversion Using Alternative Gate Symbols NOR Gate Circuit Conversion: 31
32 Circuit Conversion Using Alternative Gate Symbols Conversion of ANDOR Circuit to NAND Gates: 32
33 Circuit Conversion Using Alternative Gate Symbols Procedure to Convert to a NAND (or NOR) Circuit: 1. Convert all AND gates to NAND gates by adding an inversion bubble at the output. Convert all OR gates to NAND gates by adding inversion bubbles at the inputs. (To convert to NOR, add inversion bubbles at all ORgate outputs and all ANDgate inputs.) 2. Whenever an inverted output drives an inverted input, no further action is needed because the two inversions cancel. 3. Whenever a noninverted gate output drives an inverted gate input or vice versa, insert an inverter so that the bubbles will cancel. (Choose an inverter with the bubble at the input or output as required.) 4. Whenever a variable drives an inverted input, complement the variable (or add an inverter) so the complementation cancels the inversion at the input. 33
34 Circuit Conversion Using Alternative Gate Symbols Defection: Fanin is the number of inputs a logic gate can handle. For instance the fanin for the AND gate shown in the figure is 3. Physical logic gates with a large fanin tend to be slower than those with a small fanin. This is because the complexity of the input circuitry increases the input capacitance of the device. 34
35 Circuit Conversion Using Alternative Gate Symbols Example 3: Multilevel circuits reduce gate fanin. See the example below: 35
36 Circuit Conversion Using Alternative Gate Symbols Example 3 (continued): 36
37 Design of TwoLevel, Multiple Output Circuits Example 4: 37
38 Design of TwoLevel, Multiple Output Circuits Example 4 (continued): 38
39 Design of TwoLevel, Multiple Output Circuits Determination of Essential Prime Implicants for MultipleOutput Realization: We can find prime implicants, which are essential to one of the functions and to the multipleoutput realization by a modification of the procedure used for the singleoutput case. In particular, when we check each 1 on the map to see if it is covered by only one prime implicant, we will only check those 1 s which do not appear on the other function maps. 39
40 Design of TwoLevel, Multiple Output Circuits Determination of Essential Prime Implicants for MultipleOutput Realization: 40
41 Design of Multiple Output NANDand NOR Gate Circuits Converting a TwoOutput Circuit to NOR Gates: The procedure given in Section 7.4 for design of singleoutput, multilevel NANDand NORgate circuits also applies to multipleoutput circuits. 41
Chapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationGateLevel Minimization. BME208 Logic Circuits Yalçın İŞLER
GateLevel Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to
More informationGateLevel Minimization. section instructor: Ufuk Çelikcan
GateLevel Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to
More informationVariable, Complement, and Literal are terms used in Boolean Algebra.
We have met gate logic and combination of gates. Another way of representing gate logic is through Boolean algebra, a way of algebraically representing logic gates. You should have already covered the
More informationLecture (05) Boolean Algebra and Logic Gates
Lecture (05) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Minterms and Maxterms consider two binary variables x and y combined with an AND operation. Since eachv ariable may appear in either
More informationFollowing the advice of breaking the longest (uppermost) bar first, I'll begin by breaking the bar covering the entire expression as a first step:
DeMorgans Theorems A mathematician named DeMorgan developed a pair of important rules regarding group complementation in Boolean algebra. By group complementation, I'm referring to the complement of a
More informationBoolean Analysis of Logic Circuits
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem  IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationGate Level Minimization
Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationLSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More information(Refer Slide Time 6:48)
Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology Madras Lecture  8 Karnaugh Map Minimization using Maxterms We have been taking about
More informationLogic Gates and Boolean Algebra ENT263
Logic Gates and Boolean Algebra ENT263 Logic Gates and Boolean Algebra Now that we understand the concept of binary numbers, we will study ways of describing how systems using binary logic levels make
More informationDigital Design. Chapter 4. Principles Of. Simplification of Boolean Functions
Principles Of Digital Design Chapter 4 Simplification of Boolean Functions Karnaugh Maps Don t Care Conditions Technology Mapping Optimization, Conversions, Decomposing, Retiming Boolean Cubes for n =,
More informationEE292: Fundamentals of ECE
EE292: Fundamentals of ECE Fall 2012 TTh 10:0011:15 SEB 1242 Lecture 22 121115 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Binary Number Representation Binary Arithmetic Combinatorial Logic
More informationAustin Herring Recitation 002 ECE 200 Project December 4, 2013
1. Fastest Circuit a. How Design Was Obtained The first step of creating the design was to derive the expressions for S and C out from the given truth tables. This was done using Karnaugh maps. The Karnaugh
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationBoolean Algebra. BME208 Logic Circuits Yalçın İŞLER
Boolean Algebra BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 5 Boolean Algebra /2 A set of elements B There exist at least two elements x, y B s. t. x y Binary operators: +
More informationCombinational Logic & Circuits
WeekI Combinational Logic & Circuits Spring' 232  Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other
More informationIncompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples
Lecture B: Logic Minimization Incompletely Specified Functions with Don t Cares 2Level Transformation Review Boolean Cube KarnaughMap Representation and Methods Examples Incompletely specified functions
More informationLECTURE 4. Logic Design
LECTURE 4 Logic Design LOGIC DESIGN The language of the machine is binary that is, sequences of 1 s and 0 s. But why? At the hardware level, computers are streams of signals. These signals only have two
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationTWOLEVEL COMBINATIONAL LOGIC
TWOLEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms Tolevel simplification Boolean cubes Karnaugh maps QuineMcClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks
ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class nextnext Mon MLK Day ECE230 Review
More informationSynthesis of combinational logic
Page 1 of 14 Synthesis of combinational logic indicates problems that have been selected for discussion in section, time permitting. Problem 1. A certain function F has the following truth table: A B C
More informationPropositional Calculus. Math Foundations of Computer Science
Propositional Calculus Math Foundations of Computer Science Propositional Calculus Objective: To provide students with the concepts and techniques from propositional calculus so that they can use it to
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationA B AB CD Objectives:
Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3
More informationChapter Three. Digital Components
Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together
More information/90 TOTAL. 1(a) 8pts. fiv(a,b) is called the function.
Your Name: SID Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ Department of Electrical Engineering and Computer
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More information211: Computer Architecture Summer 2016
211: Computer Architecture Summer 2016 Liu Liu Topic: Storage Project3 Digital Logic  Storage: Recap  Direct  Mapping  Fully Associated  2way Associated  Cache Friendly Code Rutgers University Liu
More informationSimplification of Boolean Functions
Simplification of Boolean Functions Contents: Why simplification? The Map Method Two, Three, Four and Five variable Maps. Simplification of two, three, four and five variable Boolean function by Map method.
More informationChapter 3 working with combinational logic
hapter 3 working with combinational logic ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz Working with combinational logic Simplification twolevel simplification exploiting don t cares
More informationENGINEERS ACADEMY. 7. Given Boolean theorem. (a) A B A C B C A B A C. (b) AB AC BC AB BC. (c) AB AC BC A B A C B C.
Digital Electronics Boolean Function QUESTION BANK. The Boolean equation Y = C + C + C can be simplified to (a) (c) A (B + C) (b) AC (d) C. The Boolean equation Y = (A + B) (A + B) can be simplified to
More informationCombinational Logic Circuits
Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 21 Binary Logic and Gates 22 Boolean Algebra 23 Standard Forms 24 TwoLevel Circuit Optimization
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More information01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2006
Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 26 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom
More informationBasic Arithmetic (adding and subtracting)
Basic Arithmetic (adding and subtracting) Digital logic to show add/subtract Boolean algebra abstraction of physical, analog circuit behavior 1 0 CPU components ALU logic circuits logic gates transistors
More information9/10/2016. The Dual Form Swaps 0/1 and AND/OR. ECE 120: Introduction to Computing. Every Boolean Expression Has a Dual Form
University of Illinois at UrbanaChampaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Boolean Properties and Optimization The Dual Form Swaps 0/1 and AND/OR Boolean
More informationCSE303 Logic Design II Laboratory 01
CSE303 Logic Design II Laboratory 01 # Student ID Student Name Grade (10) 1 Instructor signature 2 3 4 5 Delivery Date 1 / 15  Experiment 01 (Half adder) Objectives In the first experiment, a half adder
More informationSystems Programming. Lecture 2 Review of Computer Architecture I
Systems Programming www.atomicrhubarb.com/systems Lecture 2 Review of Computer Architecture I In The Book Patt & Patel Chapter 1,2,3 (review) Outline Binary Bit Numbering Logical operations 2's complement
More information01 Introduction to Digital Logic. ENGR 3410 Computer Architecture Mark L. Chang Fall 2008
Introduction to Digital Logic ENGR 34 Computer Architecture Mark L. Chang Fall 28 Acknowledgements Patterson & Hennessy: Book & Lecture Notes Patterson s 997 course notes (U.C. Berkeley CS 52, 997) Tom
More informationSlide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationSection 001. Read this before starting!
Points missed: Student's Name: Total score: / points East Tennessee State University Department of Computer and Information Sciences CSCI 25 (Tarnoff) Computer Organization TEST 2 for Fall Semester, 25
More informationCOMP combinational logic 1 Jan. 18, 2016
In lectures 1 and 2, we looked at representations of numbers. For the case of integers, we saw that we could perform addition of two numbers using a binary representation and using the same algorithm that
More informationEEE130 Digital Electronics I Lecture #4_1
EEE130 Digital Electronics I Lecture #4_1  Boolean Algebra and Logic Simplification  By Dr. Shahrel A. Suandi 46 Standard Forms of Boolean Expressions There are two standard forms: Sumofproducts form
More information2. BOOLEAN ALGEBRA 2.1 INTRODUCTION
2. BOOLEAN ALGEBRA 2.1 INTRODUCTION In the previous chapter, we introduced binary numbers and binary arithmetic. As you saw in binary arithmetic and in the handling of floatingpoint numbers, there is
More informationGC03 Boolean Algebra
Why study? GC3 Boolean Algebra Computers transfer and process binary representations of data. Binary operations are easily represented and manipulated in Boolean algebra! Digital electronics is binary/boolean
More informationCombinational Circuits Digital Logic (Materials taken primarily from:
Combinational Circuits Digital Logic (Materials taken primarily from: http://www.facstaff.bucknell.edu/mastascu/elessonshtml/eeindex.html http://www.cs.princeton.edu/~cos126 ) Digital Systems What is a
More informationCh. 5 : Boolean Algebra &
Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying
More informationGateLevel Minimization
GateLevel Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to GateLevel Minimization The Map Method 2345 variable map methods ProductofSums Method Don t care
More information1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z
CS W3827 05S Solutions for Midterm Exam 3/3/05. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.
More informationBinary logic. Dr.AbuArqoub
Binary logic Binary logic deals with variables like (a, b, c,, x, y) that take on two discrete values (, ) and with operations that assume logic meaning ( AND, OR, NOT) Truth table is a table of all possible
More informationDepartment of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic
Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More information1. Prove that if you have tristate buffers and inverters, you can build any combinational logic circuit. [4]
HW 3 Answer Key 1. Prove that if you have tristate buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tristate buffers and inverters and thus you
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationece5745planotes.txt
ece5745planotes.txt ========================================================================== Follow up on PAL/PROM/PLA Activity ==========================================================================
More informationMODULE 5  COMBINATIONAL LOGIC
Introduction to Digital Electronics Module 5: Combinational Logic 1 MODULE 5  COMBINATIONAL LOGIC OVERVIEW: For any given combination of input binary bits or variables, the logic will have a specific
More informationChap2 Boolean Algebra
Chap2 Boolean Algebra Contents: My name Outline: My position, contact Basic information theorem and postulate of Boolean Algebra. or project description Boolean Algebra. Canonical and Standard form. Digital
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationDigital Logic Design (3)
Digital Logic Design (3) ENGG1015 1 st Semester, 2010 Dr. Kenneth Wong Dr. Hayden So Department of Electrical and Electronic Engineering Last lecture ll logic functions can be represented as (1) truth
More informationUNIT4 BOOLEAN LOGIC. NOT Operator Operates on single variable. It gives the complement value of variable.
UNIT4 BOOLEAN LOGIC Boolean algebra is an algebra that deals with Boolean values((true and FALSE). Everyday we have to make logic decisions: Should I carry the book or not?, Should I watch TV or not?
More informationClass Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitI 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
More informationUNCA CSCI 255 Exam 1 Spring February, This is a closed book and closed notes exam. It is to be turned in by 1:45 PM.
UNCA CSCI 255 Exam 1 Spring 2017 27 February, 2017 This is a closed book and closed notes exam. It is to be turned in by 1:45 PM. Communication with anyone other than the instructor is not allowed during
More informationCombinational Logic Circuits
Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical
More informationPropositional Calculus: Boolean Algebra and Simplification. CS 270: Mathematical Foundations of Computer Science Jeremy Johnson
Propositional Calculus: Boolean Algebra and Simplification CS 270: Mathematical Foundations of Computer Science Jeremy Johnson Propositional Calculus Topics Motivation: Simplifying Conditional Expressions
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationDepartment of Electrical and Computer Engineering University of Wisconsin  Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin  Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:158:3PM 1. (15 points) (a) (5 points) NAND, NOR
More information2.1 Binary Logic and Gates
1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 20062007) NOTES 5  page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationFinal Project. Project Idea. Sample Project Idea 2/11/2019. CS 362: Computer Design Lecture 7: DeMorgan s, XOR, Universal Gates
Final Project CS 362: Computer Design Lecture 7: DeMorgan s, XOR, Universal Gates Original by: Mitchell Theys University of Illinois at Chicago September 18, 2018 Groups of 2 4 Number people x requirement
More informationENEL 353: Digital Circuits Midterm Examination
NAME: SECTION: L01: Norm Bartley, ST 143 L02: Steve Norman, ST 145 When you start the test, please repeat your name and section, and add your U of C ID number at the bottom of the last page. Instructions:
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationExperimental Methods I
Experimental Methods I Computing: Data types and binary representation M.P. Vaughan Learning objectives Understanding data types for digital computers binary representation of different data types: Integers
More informationLecture (04) Boolean Algebra and Logic Gates
Lecture (4) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 26, Logic Design Boolean algebra properties basic assumptions and properties: Closure law A set S is
More informationLecture (04) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee
Lecture (4) Boolean Algebra and Logic Gates By: Dr. Ahmed ElShafee Boolean algebra properties basic assumptions and properties: Closure law A set S is closed with respect to a binary operator, for every
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More information1. Boolean algebra. [6] 2. Constructing a circuit. [4] 3. Number representation [4] 4. Adders [4] 5. ALU [2] 6. Software [4]
Family Name:.......................... Other Names:.......................... ID Number:.......................... ENGR101: Test 4 May 2009 Instructions Time allowed: 45 minutes. There are 45 marks in
More informationOptimized Implementation of Logic Functions
June 25, 22 9:7 vra235_ch4 Sheet number Page number 49 black chapter 4 Optimized Implementation of Logic Functions 4. Nc3xe4, Nb8 d7 49 June 25, 22 9:7 vra235_ch4 Sheet number 2 Page number 5 black 5 CHAPTER
More informationDigital Systems. John SUM Institute of Technology Management National Chung Hsing University Taichung, ROC. December 6, 2012
Digital Systems John SUM Institute of Technology Management National Chung Hsing University Taichung, ROC December 6, 2012 Contents 1 Logic Gates 3 1.1 Logic Gate............................. 3 1.2 Truth
More information