THIS SPEC IS OBSOLETE
|
|
- Cecil Goodman
- 6 years ago
- Views:
Transcription
1 THIS SPEC IS OBSOLETE Spec No: Spec Title: INTERFACING TI OMAPV1030 PROCESSOR TO ASTORIA'S PSEUDO-NAND PROCESSOR-PORT - AN47864 Sunset Owner: Dhanraj Rajput (DBIR) Replaced by: None
2 Interfacing TI OMAPV1030 Processor to Astoria s Pseudo-NAND Processor-port AN47864 Author: Hingkwan Huen Associated Project: No Associated Part Family: CYWB0224ABx Software Version: Astoria SDK Version Associated Application Notes: AN46712, AN46860 Application Note Abstract Cypress West Bridge Astoria provides high speed USB peripheral and mass storage control capabilities to the system processor through its host processor port. AN46712 presents a physical interconnect example of interfacing the TI OMAPV1030 baseband processor to the Astoria device, using Astoria s Pseudo-NAND Processor-port interface. Introduction The rapid growth of the mobile and embedded device market demands high speed USB connectivity and mass storage control capabilities. The Cypress West Bridge Astoria device (CYWB0224ABx) is designed to enable handset designers to easily add these functionalities to their designs. When Astoria is integrated into a system, its host Processor-port (P-port) interface is used to connect to the system bus of the principal processor. P-port on the Astoria supports multiple configurations that are compatible with a vast majority of interfaces available in many commonly used embedded processors. The Pseudo-NAND (PNAND) P-port interface is a unique feature of the Astoria. It enables the Astoria to emulate a NAND flash device. Astoria s PNAND boot feature allows a system processor to communicate with the Astoria using standard NAND commands, and boot directly from a NAND flash connected to the Astoria. The PNAND boot feature enables robust system design by consolidating boot and mass storage data in a single SLC NAND device. This feature reduces BOM cost by removing the need for having two NAND devices on the board serving different purposes: one for booting the processor and the other for mass storage. West Bridge Astoria Astoria is a flexible bridge device that uses robust SLIM architecture that allows simultaneous and independent data paths between the processor and USB, USB and mass storage, and processor and mass storage. The Processor-port (P-port) of the Astoria can operate in one of the multiple selectable interface types such as the CRAM, SRAM, Address-Data Multiplexed RAM, SPI, or PNAND. The USB-port (U-port) is a High-Speed (HS) USB peripheral that is capable of independent U P and U S data transfers with optimal performance. The mass storage-port (S-port) can be configured to simultaneously interface with multiple mass-storage devices such as 8- or 16-bit SLC NAND, Managed NAND, SD/MMC/SDIO, and CE-ATA devices. Figure 1. West Bridge Astoria Block Diagram Astoria also has the ability to allow processors to boot indirectly from SD or USB through the PNAND interface for processors that do not support the SD boot option. Using the OMAPV1030 processor as an example, this application note describes how a system processor can interface to the Astoria through the PNAND interface, and explains the considerations involved. In particular, the physical interconnect and timing considerations between OMAPV1030 and the Astoria are explained in detail. For further details of Astoria PNAND interface, supported commands, and its mode of operations, see the Astoria datasheet and the application note AN For a full description of Astoria s features, see the West Bridge Astoria datasheet. August 30, 2013 Document No Rev. *C 1
3 Astoria s PNAND Interface Astoria s P-port NAND interface is called Pseudo-NAND (PNAND) interface. Table 1 shows the PNAND signals that are mapped to P-port of the Astoria. operation is configured by changing the Astoria s internal registers. Note 1. The OMAPV1030 NFC interface only supports 8-bit data IO, IO[15:8] are do not cares and must be tied to a known state. There are two modes of operation in the PNAND interface: Logical NAND Access NonLogical NAND Access Logical NAND Access (LNA) refers to the mode of operation where the Astoria emulates a NAND flash device. This mode is designed for systems that require booting of the system processor from a NAND flash device. In this type of application, the system processor can communicate with the Astoria using common NAND commands to boot from a NAND flash connected to Astoria s S-port. In this mode of operation, the Astoria mimics a real NAND device and allows the system processor to use its internal boot-rom to boot from the Astoria, exactly as it would boot from a NAND flash. In LNA mode, the Astoria must be initialized with its attached NAND device before the system processor can access it. In nonlna mode of operation, the system processor interfaces to the Astoria using standard NAND interface, but does not use standard NAND commands. In nonlna mode, the Astoria responds to a subset of NAND commands. In this mode of operation, the system processor uses a set of APIs provided by Cypress to communicate through its NAND controller to the Astoria. The nonlna mode of operation can be used independent of the PNAND LNA boot. When Astoria is used in PNAND LNA mode, its available features are limited to the transfers between P-port and U-port, and NAND flash access on the S-port. To take advantage of Astoria s features, the system must switch from LNA to nonlna mode of operation. This is done by setting a register after booting is complete. The register setting is handled through the APIs. Although P U access is available in LNA mode, Astoria APIs must be used to access this feature. The PNAND interface of Astoria can be configured to support one of the following modes: 8-bit small block device (SBD) 8-bit large block device (LBD) 16-bit SBD 16-bit LBD In SBD mode, there is one address cycle for the column address and three address cycles for the row address whereas in LBD mode, there are two address cycles for the column address and three address cycles for the row address. Moreover, in SBD mode, the acceptable commands are 00h, 01h, or 50h whereas in LBD mode, the only command is 00h. SBD or LBD mode is configured through the external pin settings shown in Table 2. The 8 versus 16-bit mode of August 30, 2013 Document No Rev. *C 2
4 Table 2 Table 1. Astoria PNAND Interface Signals and Example Connection to OMAPV1030's NFC Interface P-port Signal Name IO Alias PNAND Signal Name OMAPV1030 NFC Interface Pins CE# I CE# nfls_ce1 or nfls_ce2 Chip enable Function A[0] I CLE nfls_cle Command latch enable Comments A[1] O R/B# nfls_rdy Ready/Busy# This signal is NOT open-drained A[3:2] I A[3:2] - PNAND mode select A[3:2]=0b00 A[4] I WP# - Write protect Optional A[5] O SCL - I 2 C serial clock Used for EEPROM boot. Pull-up needed A[6] IO SDA - I 2 C serial data Used for EEPROM boot. Pull-up needed A[7] I SDBnLBD - SDB or LBD select SDB if A[7]=1; LBD if A[7]=0 DQ[15:0] IO IO[15:0] nfls_fd[7:0] Data bus Supports 8-bit or 16-bit mode ADV# I ALE nfls_ale Address latch enable OE# I RE# nfls_re Read enable WE# I WE# nfls_we Write enable INT# O INT# GPIOx Astoria device interrupt Used only in nonlna mode DRQ# O DRQ# - DMA request Optional. Used only in nonlna mode TEST[2:0] I TEST[2:0] - Mode configuration TEST[2:0]=0b010 for PNAND Note 1. The OMAPV1030 NFC interface only supports 8-bit data IO, IO[15:8] are do not cares and must be tied to a known state. August 30, 2013 Document No Rev. *C 3
5 Table 2. PNAND Mode Configuration Pin Setting Mode TEST[2] TEST[1] TEST[0] A[7] A[3] A[2] SBD LBD Interface to OMAPV1030 through PNAND The OMAPV1030 E-GPRS baseband processor belongs to the Texas Instruments OMAP-Vox processor family. It combines a communication engine, an application engine, and a digital signal processing (DSP) subsystem. The DSP subsystem delivers enhanced multimedia performance and communication capability for the handset designers who want to develop a cost-efficient GSM/GPRS/EDGE solution for mainstream wireless users. Among OMAPV1030 s memory interfaces, the external memory interface slow (EMIFS) and NAND flash controller (NFC) interface are both compatible with the Astoria s PNAND interface. OMAPV1030 s EMIFS interface can emulate a NAND flash interface through software. In this case, the Figure 2 shows an example of a connection between the OMAPV1030 processor and the Astoria. processor supports both 8-bit and 16-bit NAND devices. However, one drawback is the additional processing power required for the emulation. By using OMAPV1030 s embedded NFC interface, although it supports only 8-bit NAND devices, a simpler setup and gain in MIPS consumption is offered, comparing to the EMIFS NAND emulation option. The example presented in this application note uses the NFC interface to interconnect OMAPV1030 with the Astoria. This is because it is easier to configure with the additional benefit of using the hardware NAND controller of the processor. The OMAPV1030 s embedded NFC interface allows seamless connection to the Astoria s P-port in PNAND configuration. Figure 2. Example of a Connection between OMAPV1030 s NFC Interface and Astoria s P-Port in PNAND Mode I2C EEPROM SCL SDA nfls_rdy R/B# GPIOx INT# OMAPV1030 Processor NFC Interface nfls_fd[7:0] nfls_re nfls_we nfls_ce1 or nfls_ce2 nfls_ale IO[7:0] RE# WE# CE# ALE P-Port West Bridge Astoria U-Port High Speed USB nfls_cle CLE S-Port NAND Flash August 30, 2013 Document No Rev. *C 4
6 The basic modes of operations of the Astoria PNAND interface are the same as common NAND devices, which include: Bus Operations The bus on the Astoria PNAND is internally multiplexed. Data IO, addresses, and commands share the same IO pins. IO[15:8] are used only for data in the x16 configuration. Addresses and commands are always supplied on IO[7:0]. Because the NFC interface of the OMAPV1030 only supports 8-bit data IO, IO[15:8] are do not cares and must be tied to a known state. The command sequence normally consists of a command latch cycle, an address latch cycle, and a data cycle - either read or write. Control Signals The signals CE#, WE#, RE#, CLE, and ALE control flash device READ and WRITE operations. CE# is used to enable the device. When CE# is low and the device is not in the busy state, the flash memory accepts command, data, and address information. When the device is not performing an operation, the CE# pin is typically driven HIGH and the Astoria is inactive. Commands (ALE=0, CLE=1) All the NAND operations (except READ STATUS and RESET commands) consist of a command write cycle followed by an address write cycle. The READ STATUS command does not have an address write cycle. The command is transferred into the NAND command register followed by the start address for the read or program operation, latched into the address register. Commands are written to the command register on the rising edge of WE# when CE# and ALE are low, and CLE is high. Commands are input on IO[7:0]. Address (ALE = 1, CLE = 0) Addresses are written to the address register on the rising edge of WE# when CE# and CLE are low, and ALE is high. Addresses are input on IO[7:0]. Data (ALE = 0, CLE = 0) Data is written to the data register on the rising edge of WE# when CE#, CLE, and ALE are low. Data is input on IO[7:0]. Ready / Busy The R/B# output from the Astoria provides a hardware method of indicating the completion of a PROGRAM/ERASE/READ operation. The signal is typically high, and transitions to low after the appropriate command is written to the device. Because R/B# signal in the Astoria is not open-drained, there is no need to include a pull-up resistor for proper operation of this pin. Figure 3 shows the example waveform of the successive accesses: COMMAND Latch, ADDRESS Latch, and DATA Output. Note that the commands cannot be sent to the NAND flash during tr, because it is busy. Figure 3. Astoria PNAND Page Read Operation See the Astoria s datasheet and AN46712 for supported command sets and full operation description of PNAND interface. August 30, 2013 Document No Rev. *C 5
7 OMAPV1030 NFC Interface Configuration Clocking The OMAPV1030 NFC module is clocked by a functional clock (NDFLASH_FLCK) and an interface clock (NDFLASH_ICLK). Both clocks are driven by the processor s MPU peripheral clock (ARMPER_CK) derived from the OMAP3.4 clock generator one module (CLKM1). The ARMPER_CK clock frequency can be programmed through the ARM_CLKCTL[0:1] register mapped into the OMAPV1030 MPU address space. Because each system may have a different setting for the ARMPER_CK, this application note assumes that: ARMPER_CK frequency =130 MHz That is, ARMPER_CK period = 7.7 ns If ARMPER_CK runs at a different frequency, the interface timing must be re-evaluated, but the principle of the analysis remains the same. Timing Registers To correctly interface the OMAPV1030 processor to the Astoria, the OMAPV1030 NFC registers must be configured. Table 3 shows the list of NFC timing registers that need to be configured. Table 3. OMAPV1030 NFC Interface Timing Registers Register Name NND_PSC_CLK NND_PSC1_CLK NND_PSC2_CLK MPU Mapped Address 0xFFFBCC5C 0xFFFBCC8C 0xFFFBCC90 Description A 4-bit value in this register divides the interface clock to adjust the timing for signals on the physical interface NAND controller clock prescale register HIGH NAND controller clock prescale register SAMPLE compatibility with other OMAP devices (for example, OMAP1610), any value written to the NND_PSC_CLK register is copied into both NND_PSC1_CLK and NND_PSC2_CLK. As a result, NND_PSC1_CLK and NND_PSC1_CLK must be written after the NND_PSC_CLK. Timing Analysis and Recommendations This section provides a timing analysis summary between the OMAPV1030 and the Astoria. Table 4 on page 5 shows the OMAPV1030 NFC s interface timing specifications. The specification values are converted in terms of timing register values for easier calculation of the recommended final program values. An accurate one to one comparison is necessary between the OMAPV1030 NFC interface and the Astoria PNAND waveforms. Figure 4 and Figure 5 on page 5 show two cases that highlight all the required timings. Table 5 on page 6 presents compatible timing parameters and calculations for the required register configurations. Based on these calculations, the recommended OMAPV1030 NFC interface register settings are: X = NND_PSC_CLK register value = 0x3; Y = NND_PSC1_CLK register value = 0x1; Z = NND_PSC2_CLK register value = 0x0. To determine the throughput and optimization of the interface with a particular processor, contact your local Cypress sales representative. The NND_PSC1_CLK and NND_PSC2_CLK registers are used with the NND_PSC_CLK register to control the memory interface timing. To maintain backward August 30, 2013 Document No Rev. *C 6
8 Table 4. OMAPV1030 NFC Interface Timing Specifications Symbol OMAPV1030 Parameter Description OMAPV1030 Spec OMAPV1030 Spec in Terms of Register Value Min (ns) Max (ns) Min (ns) Max (ns) NFC1 tw(wev) nfls_we low duration P-1.5 P+1.5 (X+1)* (X+1)* NFC2 tw(weiv) nfls_we high duration Q-1.5 Q+1.5 (Y+1)* (Y+1)* NFC3 NFC4 NFC5 NFC6 NFC7 td(clev-wev) td(wev-iov) td(weiv-clel) td(alev-wev) td(weiv-alel) Delay time, nfls_cle high to nfls_we low Delay time, nfls_we high to nfls_fd valid Delay time, nfls_we high to nfls_cle low Delay time, nfls_ale high to nfls_we low Delay time, nfls_we high to nfls_ale low P-1.4 P+1.9 (X+1)* (X+1)* P-1.5 P+1.9 (X+1)* (X+1)* NFC8 tw(rev) nfls_re low duration P-1.7 P+1.7 (X+1)* (X+1)* NFC9 tw(reiv) nfls_re high duration Q-1.7 Q+1.7 (Y+1)* (Y+1)* NFC10 NFC11 tsu(iov-reh) th(reh-iov) Setup time, nfls_fd[7:0] valud before nfls_re hgih Hold time, nfls_fd[7:0] valud after nfls_re hgih Notes 1. Let X=NND_PSC_CLK register value; Y=NND_PSC1_CLK register value; Z=NND_PSC2_CLK register value 2. P = (X + 1) * ARMPER_CK clock cycles 3. Q = (Y + 1) * ARMPER_CK clock cycles 4. N = (Z - X) * ARMPER_CK clock cycles 9.6-N (Z-X)* Figure 4. Command Latch and Address Latch Cycle (Astoria vs. OMAPV1030) Figure 5. Serial Read Access Cycle (Astoria vs. OMAPV1030) August 30, 2013 Document No Rev. *C 7
9 Table 5. Astoria and OMAPV1030 NFC Timing Analysis and Calculations Timing Astoria Name Description Setup Hold Pulse Width tcls tals tcs tds trp - trea + 2*board delay tcea trea trr CLE Setup ALE Setup CE# Setup Data Setup Data Output Setup CE# Access Register/EP Access Ready/Busy# to RE LOW Astoria Min [ns] 15 5 Astoria Max [ns] OMAPV1030 Parameter td(clev-wev)min + tw(wev)min td(alev-wev)min + tw(wev)min 20 Not programmable 15 tw(wev)min - td(wev-iov)max -13 tsu(iov-reh) 35 Not programmable 30 Not programmable 20 Managed by software tclh CLE Hold 5 td(weiv-clel)min talh ALE Hold 5 td(weiv-alel)min tch CE# Hold 5 Not programmable tdh toh treh twp trp twc trc Data Hold Data Output Hold RE# High Hold WE# Pulse Width RE# Pulse Width Write Cycle Read Cycle 5 tw(weiv)min td (WEV-IOV)max Calculated NFC Configuration (-1.9)+(X+1)* > 15 => X = 2 (-1.9)+(X+1)* > 5 => X = 1 Guaranteed by tcls and tals (X+1)* > 15 => X = (Z-X)*7.7 < -13 => X = 3; Z = 0 (X+1)* > 5 => X = 0 (X+1)* > 5 => X = 1 (Y+1)* > 5 => Y = 0 15 th(reh-iov)min Always met 10 tw(reiv)min 15 tw(wev)min 15 tw(rev)min 30/33 (Note 1) 30/33 (Note 1) Notes ns for Astoria VFBGA package; 33 ns for Astoria WLCSP package. 2. Assume board delay of 1 ns. tw(wev)min + tw(weiv)min tw(rev)min + tw(reiv)min (Y+1)* > 10 => Y = 1 (X+1)* > 15 => X = 3 (X+1)* > 15 => X = 3 (X+1)* (Y+1)* > 33 => X = 3; Y = 0 (X+1)* (Y+1)* > 33 => X = 3; Y = 0 Summary Astoria can be effectively interconnected with TI OMAPV1030 baseband processor through the Astoria s PNAND interface. The timing analysis described in this application note affirms the mode of operations supported with the Astoria. The integration of the Astoria device through a PNAND interface is advantageous for the OMAPV1030 based system designs. It provides popular USB connectivity and mass storage control capabilities, and also allows the processor to use conventional NAND booting option with the Astoria device. The timing analysis and recommended timing numbers for the OMAPV1030 hardware NAND controller interface are also documented here. August 30, 2013 Document No Rev. *C 8
10 Additional Resources West Bridge Astoria Advance Datasheet OMAPV1030 Product Bulletin Interfacing to West Bridge Astoria's Pseudo-NAND Processor Port AN46712 Schematic Review Checklist for West Bridge Astoria - AN46860 About the Author Name: Hingkwan Huen Title: Contact: DCD Applications Engineer hkh@cypress.com August 30, 2013 Document No Rev. *C 9
11 Document History Document Title: Interfacing TI OMAPV1030 Processor to Astoria s Pseudo-NAND Processor-port AN47864 Document Number: Revision ECN Orig. of Change Submission Date Description of Change ** HKH/AESA 08/04/2008 New application note. *A ANOP 03/02/2011 Updated Astoria SDK Version, Updated Introduction, West Bridge Astoria Sections and Table 1, Added Additional Resources section. *B ODC 07/28/2011 Updated Associated Application Notes and broken links. *C RSKV 08/30/2013 Obsolete application note SLIM and West Bridge is registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA Phone: Fax: Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. August 30, 2013 Document No Rev. *C 10
Use the Status Register when the firmware needs to query the state of internal digital signals.
1.60 Features Up to 8-bit General Description The allows the firmware to read digital signals. When to Use a Use the when the firmware needs to query the state of internal digital signals. Input/Output
Use the Status Register when the firmware needs to query the state of internal digital signals.
1.70 Features Up to 8-bit General Description The allows the firmware to read digital signals. When to Use a Use the when the firmware needs to query the state of internal digital signals. Input/Output
This optional pin is present if the Mode parameter is set to SyncMode or PulseMode. Otherwise, the clock input does not show.
1.60 Features Up to 8-bit General Description The allows the firmware to output digital signals. When to Use a Use a when the firmware needs to interact with a digital system. You can also use the as a
THIS SPEC IS OBSOLETE
THIS SPEC IS OBSOLETE Spec Number: 001-65252 Spec Title: AN1071 Single Versus Multiple Transaction Translator Sunset Owner: RSKV Replaced By: None Single Versus Multiple Transaction Translator Application
Cypress HX2VL Configuration Utility Blaster User Guide
Cypress HX2VL Configuration Utility Blaster User Guide Spec. # 001- Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
Writing to Internal Flash in PSoC 3 and PSoC 5
Writing to Internal Flash in PSoC 3 and PSoC 5 Code Example Objective CE62384 demonstrates how to write to the internal flash to change its contents during run time. CE62384 Associated Part Families: CY8C3xxx
HX2VL Development Kit Guide. Doc. # Rev. *A
HX2VL Development Kit Guide Doc. # 001-73960 Rev. *A Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights
This optional pin is present if the Mode parameter is set to SyncMode or PulseMode. Otherwise, the clock input does not show.
1.70 Features Up to 8-bit General Description The allows the firmware to output digital signals. When to Use a Use a when the firmware needs to interact with a digital system. You can also use the as a
AN EZ-USB FX3 I 2 C Boot Option. Application Note Abstract. Introduction. FX3 Boot Options
EZ-USB FX3 I 2 C Boot Option Application Note Abstract AN68914 Author: Shruti Maheshwari Associated Project: No Associated Part Family: EZ-USB FX3 Software Version: None Associated Application Notes: None
HX2VL Development Kit Guide. Doc. # Rev. **
HX2VL Development Kit Guide Doc. # 001-73960 Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights
Cypress HX2VL Configuration Utility Blaster User Guide
Cypress HX2VL Configuration Utility Blaster User Guide Doc. # 001-70672 Rev. *B Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
CE56273 Associated Part Families: CY8C38xx/CY8C55xx Software: PSoC Creator Related Hardware: CY8CKIT-001 Author: Anu M D
Objective CE56273 SPI With DMA in PSoC 3 / PSoC 5 CE56273 Associated Part Families: CY8C38xx/CY8C55xx Software: PSoC Creator Related Hardware: CY8CKIT-001 Author: Anu M D This code example demonstrates
THIS SPEC IS OBSOLETE
THIS SPEC IS OBSOLETE Spec No: 002-04992 Spec Title: Installation of the LAN Adapter Replaced by: NONE Installation of the LAN Adapter Doc. No. 002-04992 Rev. *A Cypress Semiconductor 198 Champion Court
CE PSoC 4: Time-Stamped ADC Data Transfer Using DMA
CE97091- PSoC 4: Time-Stamped ADC Data Transfer Using DMA Objective This code example uses a DMA channel with two descriptors to implement a time-stamped ADC data transfer. It uses the Watch Dog Timer
Filter_ADC_VDAC_poll Example Project Features. General Description. Development Kit Configuration
1.10 Features FIR low-pass filter at 6 khz with Blackman window, 85 taps Demonstrates the polling mode of the Filter component AC-coupled input provided bias with internal Opamp for maximum swing DMA used
PSoC 1 I 2 C Bootloader
Objective Project Name: PSoC1_I2C_Bootloader Programming Language: C Associated Part: All PSoC 1 Families Software Version: PD 5.2 SP1 Related Hardware: CY3210 PSoC Eval1 Board Author: Jie Yuan This project
GPIF II Designer - Quick Start Guide
GPIF II Designer - Quick Start Guide 1. Introduction Welcome to GPIF II Designer - a software tool to configure the processor port of EZ-USB FX3 to connect to any external device. This application generates
CY7C603xx CYWUSB
Datasheet CMP V 1.2 001-13261 Rev. *J Comparator Copyright 2001-2012 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT Analog SC Flash RAM
Reviving Bit-slice Technology in a Programmable Fashion
By Andrew Siska, Applications Engineer Sr Staff, and Meng He, Product Marketing Engineer Sr, Cypress Semiconductor Corp. The term Bit Slicing was once dominant in history books as a technique for constructing
Voltage Reference (Vref) Features. General Description. Input/Output Connections. When to Use a Vref Voltage references and supplies
PSoC Creator Component Datasheet Voltage Reference (Vref) 1.60 Features Voltage references and supplies Multiple options Bandgap principle to achieve temperature, and voltage stability General Description
THIS SPEC IS OBSOLETE
THIS SPEC IS OBSOLETE Spec No: 001-17581 Spec Title: WIRELESSUSB(TM) LP RDK JAPANESE RADIO LAW TESTING AND VERIFICATION - AN17581 Replaced by: NONE AN17581 WirelessUSB LP RDK Japanese Radio Law Testing
Comparator (Comp) Features. General Description. When to use a Comparator 1.60
1.60 Features Low input offset User controlled offset calibration Multiple speed modes Low power mode Output routable to digital logic blocks or pins Selectable output polarity Configurable operation mode
For one or more fully configured, functional example projects that use this user module go to
Datasheet RefMux V 1.3 001-13584 Rev. *H Reference Multiplexer Copyright 2003-2012 Cypress Semiconductor Corporation. All Rights Reserved. PSoC Blocks API Memory (Bytes) Resources Digital Analog CT Analog
8 to 1 Analog Multiplexer Datasheet AMux8 V 1.1. Features and Overview
Datasheet AMux8 V 1.1 001-13257 Rev. *J 8 to 1 Analog Multiplexer Copyright 2001-2015 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT
AN SIO Tips and Tricks in PSoC 3 / PSoC 5. Application Note Abstract. Introduction
SIO Tips and Tricks in PSoC 3 / PSoC 5 Application Note Abstract AN60580 Author: Pavankumar Vibhute Associated Project: Yes Associated Part Family: CY8C38xxxx Software Version: PSoC Creator Associated
12-Mbit (512 K 24) Static RAM
12-Mbit (512 K 24) Static RAM Features High speed t AA = 10 ns Low active power I CC = 175 ma at 10 ns Low CMOS standby power I SB2 = 25 ma Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic
Next-Generation Hot-Swap Controllers
Next-Generation Hot-Swap Controllers By Jim Davis, Product Mktg Engineer Staff, Cypress Semiconductor Corp. Current hot-swap controllers are great at what they do: simple yet reliable monitoring of critical
4 to 1 Analog Multiplexer Data Sheet
26. 4 to 1 Analog Multiplexer Copyright 2001-2009 Cypress Semiconductor Corporation. All Rights Reserved. 4 to 1 Analog Multiplexer Data Sheet 4 to 1 MUX Resources CY8C29/27/24/22/21xxx, CY8C23x33, CY8CLED02/04/08/16,
Programmable Threshold Comparator Data Sheet
10. Programmable Threshold Comparator Programmable Threshold Comparator Data Sheet Copyright 2001-2009 Cypress Semiconductor Corporation. All Rights Reserved. CMPPRG Resources CY8C29/27/24/22xxx, CY8C23x33,
AN1090. NoBL : The Fast SRAM Architecture. Introduction. NoBL SRAM Description. Abstract. NoBL SRAM Operation
AN1090 NoBL : The Fast SRAM Architecture Associated Project: No Associated Part Family: All NoBL SRAMs Software Version: None Related Application Notes: None Abstract AN1090 describes the operation of
FTG Programming Kit CY3670. Spec. # Rev. *C
CY3670 Spec. # 38-07410 Rev. *C Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights Copyrights Cypress
CYClockMaker Programming Kit Guide CY3675. Doc. # Rev. **
CY3675 CYClockMaker Programming Kit Guide Doc. # 001-52414 Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
EZ-USB FX3 Development Kit Guide
CYUSB3KIT-001 EZ-USB FX3 Development Kit Guide Doc. #: 001-70237 Rev. *A Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
CYClockMaker Programming Kit Guide CY3675. Doc. # Rev. *C
CY3675 CYClockMaker Programming Kit Guide Doc. # 001-52414 Rev. *C Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
This Application Note demonstrates an SPI-LIN slave bridge using a PSoC device. Demonstration projects are included.
Communication - SPI-LIN Slave Bridge Application Note Abstract AN0 Author: Valeriy Kyrynyuk Associated Project: Yes Associated Part Family: CY8C7 GET FREE SAMPLES HERE Software Version: PSoC Designer.
The following table lists user modules used in this code example and the hardware resources occupied by each user module.
CSA Software Filters with EzI2Cs Slave on CY8C20xx6 CE63794 Code Example Name: Example_CSA_EzI 2 Cs_Filters_20xx6 Programming Language: C Associated Part Families: CY8C20xx6 Software Version: PD5.1 (SP2)
Use the IDAC8 when a fixed or programmable current source is required in an application.
PSoC Creator Component Data Sheet 8-Bit Current Digital to Analog Converter (IDAC8) 1.50 Features Three ranges 2040 ua, 255 ua, and 32.875 ua Software or clock driven output strobe Data source may be CPU,
PSoC 4 Low Power Comparator (LPComp) Features. General Description. When to Use a LPComp 2.0. Low input offset. User controlled offset calibration
2.0 Features Low input offset User controlled offset calibration Multiple speed modes Low-power mode Wake from low power modes Multiple interrupt and output modes General Description The Low Power Comparator
144-Mbit QDR -II SRAM 2-Word Burst Architecture
ADVAE Y71610V, Y71625V Y71612V, Y71614V 144-Mbit QDR -II SRAM 2-Word Burst Architecture Features Separate independent read and write data ports Supports concurrent transactions 333 MHz clock for high bandwidth
CY3660-enCoRe V and encore V LV DVK Kit Guide
CY3660-enCoRe V and encore V LV DVK Kit Guide Doc. # 001-41500 Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
Preliminary. Gas Sensor Analog Front End Datasheet GasSensorAFE V Features and Overview. This datasheet contains Preliminary information.
Preliminary Gas Sensor Analog Front End Datasheet GasSensorAFE V 1.10 001-81375 Rev. *A GasSensorAFE Copyright 2012-2013 Cypress Semiconductor Corporation. All Rights Reserved. This datasheet contains
Shadow Registers Datasheet ShadowRegs V 1.1. Features and Overview
Datasheet ShadowRegs V 1.1 001-16962 Rev. *H Shadow Registers Copyright 2007-2013 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT Analog
LPF (Optional) CY8C24x93. Without LPF and ISR to 3* With LPF only** to 3* With ISR only to 3*
Datasheet CMP V 1.00 001-85893 Rev. ** Comparator Copyright 2013 Cypress Semiconductor Corporation. All Rights Reserved. PSoC Resources API Memory (Bytes) UM Configurations CMP LPF (Optional) Analog Interrupt
16-Bit Hardware Density Modulated PWM Data Sheet
1. 16-Bit Hardware Density Modulated PWM User Module Data Sheet 16-Bit Hardware Density Modulated PWM Data Sheet DMM16HW DMM16HW Copyright 2009 Cypress Semiconductor Corporation. All Rights Reserved. PSoC
Clock Programming Kit
Clock Programming Kit Clock Programming Kit Features Supports these field-programmable clock generators: CY2077FS, CY2077FZ, CY22050KF, CY22150KF, CY22381F, CY22392F, CY22393F, CY22394F, CY22395F, CY23FP12,
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores
4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features True dual-ported memory cells, which allow simultaneous reads of the same memory location 4K x 8 organization 0.65 micron
DMX512 Receiver Datasheet DMX512Rx V 1.0. Features and Overview
Datasheet DMX512Rx V 1.0 001-14404 Rev. *G DMX512 Receiver Copyright 2007-2014 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT Analog
CE58957 demonstrates how to implement the fade and toggle feature to the backlight LEDs of CapSense buttons.
Objective CapSense Sigma Delta (CSD) with LED Backlight Fading on CY8C24x94 CE58957 Code Example Name: Example_CSD_BacklightFading_24x94 Programming Language: C Associated Part Families: CY8C24x94 Software
PSoC Programmer 3.12 Release Notes
PSoC Programmer 3.12 Release Notes Release Date: July 28, 2010 Thank you for your interest in PSoC Programmer 3.12. These release notes list all new features, installation requirements, supported devices
Supported Devices: CY8C28x13, CY8C28x33, CY8C28x43, CY8C28x45, CY8C28x52, CY8C21x45, CY8C22x45, CY8C24x93. CY8C24x
Current DAC Datasheet IDAC V 1.00 001-85892 Rev. ** 6-Bit Voltage Output DAC Copyright 2013 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog
PSoC Creator Component Datasheet
1.30 Features Supports 4-wire resistive touchscreen interface Supports the Delta Sigma Converter for both the PSoC 3 and PSoC 5 devices Supports the ADC Successive Approximation Register for PSoC 5 devices
The color of the Clock component waveform symbol will change based on the clock's domain (as shown in the DWR Clock Editor), as follows:
1.60 Features Quickly defines new clocks Refers to system or design-wide clocks Configures the clock frequency tolerance General Description The component provides two key features: it provides allows
Programmer User Guide
Programmer User Guide Programmer Guide 3.06 Spec. # 001-51796 Rev. *A Cypress Semiconductor 3901 North First Street San Jose, CA 95134 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
24-Bit Pseudo Random Sequence Generator Data Sheet
48. 24-Bit Pseudo Random Sequence Generator 24-Bit Pseudo Random Sequence Generator Data Sheet Copyright 2000-2009 Cypress Semiconductor Corporation. All Rights Reserved. PRS24 PSoC Blocks API Memory (Bytes)
Programmable Gain Amplifier Datasheet PGA V 3.2. Features and Overview
Datasheet PGA V 3.2 001-13575 Rev. *I Programmable Gain Amplifier Copyright 2002-2014 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT
GPIF II Designer 1.0. Doc. No Rev. **
GPIF II Designer 1.0 Doc. No. 001-75664 Rev. ** Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com Copyrights
EZ I 2 C Slave. Features. General Description. When to use a EZ I 2 C Slave 1.50
PSoC Creator Component Data Sheet EZ I 2 C Slave 1.50 Features Industry standard Philips I 2 C bus compatible interface Emulates common I 2 C EEPROM interface Only two pins (SDA and SCL) required to interface
FM3 MB9B100A/300A/400A/500A Series Inverter Solution GUI User Guide
FM3 MB9B100A/300A/400A/500A Series Inverter Solution GUI User Guide Doc. No. 002-04375 Rev. *A Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 http://www.cypress.com Copyrights Copyrights
CapSense I 2 C/SPI Timer Flash RAM
Datasheet SPIS V 2.5 001-13679 Rev. *K SPI Slave Copyright 2002-2015 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) CapSense I 2 C/SPI Timer Flash RAM
Use the Status Register when the firmware needs to query the state of internal digital signals.
PSoC Creator Component Datasheet Status Register 1.80 Features Up to 8-bit Status Register Interrupt support General Description The Status Register allows the firmware to read digital signals. When to
Automatic reload of the period to the count register on terminal count
1.0 Features 7-bit read/write period register 7-bit count register that is read/write Automatic reload of the period to the count register on terminal count Routed load and enable signals General Description
Use the Status Register when the firmware needs to query the state of internal digital signals.
1.50 Features Up to 8-bit General Description The allows the firmware to read digital signals. When to Use a Use the when the firmware needs to query the state of internal digital signals. Input/Output
PSoC Designer Release Notes
Version 5.4 Content Pack 1 Release Date: 14 July 2014 Thank you for your interest in PSoC Designer. PSoC Designer is a complete Integrated Development Environment (IDE) for designing with PSoC 1 devices.
Incremental ADC Data Sheet
4. Incremental ADC Incremental ADC Data Sheet Copyright 2008-2009 Cypress Semiconductor Corporation. All Rights Reserved. ADCINC PSoC Resources Blocks API Memory Pins (per CapSense I2C/SPI Timer Comparator
1-Mbit (64K x 16) Static RAM
1-Mbit (64K x 16) Static RAM Features Temperature ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C Pin and function compatible with CY7C1021BV33
CE95314 PSoC 3, PSoC 4, and PSoC 5LP EZI2C
CE95314 PSoC 3, PSoC 4, and PSoC 5LP EZI2C Objective These code examples demonstrate the usage of the EZI2C slave and I 2 C master Components in PSoC 3, PSoC 4, and PSoC 5LP. Overview These code examples
West Bridge : Astoria USB and Mass Storage Peripheral Controller
West Bridge : Astoria USB and Mass Storage Peripheral Controller West Bridge : Astoria USB and Mass Storage Peripheral Controller Features Multimedia device support Up to two SD, SDIO, MMC, MMC+, and CE-ATA
This optional pin is present if the Mode parameter is set to SyncMode or PulseMode. Otherwise, the clock input does not show.
1.50 Features Up to 8-bit General Description The allows the firmware to output digital signals. When to Use a Use a when the firmware needs to interact with a digital system. You can also use the as a
Digital Logic Gates. Features. General Description. Input/Output Connections. When to Use a Logic Gate. Input 1. Input 2. Inputs 3-8 * 1.
1.0 Features Industry-standard logic gates Configurable number of inputs up to 8 Optional array of gates General Description Logic gates provide basic boolean operations. The output of a logic gate is
This input determines the next value of the output. The output does not change until the next rising edge of the clock.
1.30 Features Asynchronous reset or preset Synchronous reset, preset, or both Configurable width for array of s General Description The stores a digital value. When to Use a Use the to implement sequential
H O S T. FX2 SX2 Back - to - Back Setup. Project Objective. Overview
FX2 SX2 Back - to - Back Setup Project Objective Project Name: FX2_SX2 Programming Language: C Associated Part Families: CY7C68013A,CY7C68001 Software Version: Keil µvision2 Related Hardware: CY3682/CY3684
This section describes the various input and output connections for the SysInt Component.
1.0 Features Generating interrupts from hardware signals Assigning interrupts to a CPU core Configuring interrupt priority Interrupt vectoring and control General Description The Component is a graphical
Digital Multiplexer and Demultiplexer. Features. General Description. Input/Output Connections. When to Use a Multiplexer. Multiplexer 1.
PSoC Creator Component Datasheet Digital Multiplexer and Demultiplexer 1.10 Features Digital Multiplexer Digital Demultiplexer Up to 16 channels General Description The Multiplexer component is used to
For More Information Please contact your local sales office for additional information about Cypress products and solutions.
The following document contains information on Cypress products. The document has the series name, product name, and ordering part numbering with the prefix MB. However, Cypress will offer these products
4-Mbit (256K x 16) Static RAM
4-Mbit (256K x 16) Static RAM Features Temperature ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive-A: 40 C to 85 C Automotive-E: 40 C to 125 C Pin and function compatible with CY7C1041BV33
Capable of adjusting detection timings for start bit and data bit
PSoC Creator Component Datasheet Remote Control (PDL_RC) 1.0 Features Up to 2 Channels HDMI-CEC/ High Definition Multimedia Interface Consumer Electronics Control transmitter/receiver SIRCS/Sony Infrared
This section describes the various input and output connections for the Voltage Fault Detector.
PSoC Creator Component Datasheet Voltage Fault Detector (VFD) 2.10 Features monitor up to 32 voltage inputs user-defined over and under voltage limits simply outputs a good/bad status result General Description
Bootloader project - project with Bootloader and Communication components
PSoC Creator Component Datasheet Bootloader and Bootloadable 1.10 Features Separate Bootloader and Bootloadable components Configurable set of supported commands Flexible component configuration General
Libraries Guide. Arithmetic Libraries User Guide. Document #: Rev. *A
Libraries Guide Arithmetic Libraries User Guide Document #: 001-44477 Rev. *A Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
AN F²MC-16FX Family, I2C. Contents. 1 Introduction. This application note describes how to communicate via I2C with a Serial EEPROM.
AN204776 This application note describes how to communicate via I2C with a Serial EEPROM. Contents 1 Introduction... 1 2 24C04... 2 2.1 EEPROM... 2 2.2 Connection to MB963xx... 3 2.3 Addressing... 3 2.4
Supports a range of speeds of external memories (from 5 to 200 ns) Supports external memory power-down, sleep, and wakeup modes
PSoC Creator Component Datasheet External Memory Interface (EMIF) 1.30 Features 8-, 16-, 24-bit address bus width 8-, 16-bit data bus width Supports external synchronous memory Supports external asynchronous
EZ-USB NX2LP USB 2.0 NAND Flash Controller
EZ-USB NX2LP USB 2.0 NAND Flash Controller EZ-USB NX2LP USB 2.0 NAND Flash Controller Features High-Speed (480-Mbps) or Full-Speed (12-Mbps) USB support Both common NAND page sizes supported 512 bytes
Multifunction Serial Interface (PDL_MFS) Features. General Description. When to Use a PDL_MFS Component. Quick Start 1.0
1.0 Features Configures the Multi-Function Serial (MFS) Interface to one of the following modes: UART (Asynchronous normal serial interface) Clock synchronous serial interface (SPI and I 2 S can be supported)
Release Notes SRN065 PSoC Programmer Version Release Date: November 9, 2009
Release Notes SRN065 PSoC Programmer Version 3.10.1 Release Date: November 9, 2009 Thank you for your interest in PSoC Programmer version 3.10. These release notes list the installation requirements and
PSoC Programmer Release Notes
PSoC Programmer Release Notes Version 3.16 Release Date: September 12, 2012 Thank you for your interest in the PSoC Programmer. The release notes lists all the new features, installation requirements,
Base Timer Channel (BT) Features. General Description. When to Use a PDL_BT Component 1.0
1.0 Features Four operating modes 16-bit PWM Timer 16-bit PPG Timer 16/32-bit Reload Timer 16/32-bit PWC Timer Trigger generation for ADC conversion General The Peripheral Driver Library (PDL) Base Timer
Use a DieTemp component when you want to measure the die temperature of a device.
PSoC Creator Component Datasheet Die Temperature (DieTemp) 2.0 Features Accuracy of ±5 C Range 40 C to +140 C (0xFFD8 to 0x008C) Blocking and non-blocking API General Description The Die Temperature (DieTemp)
Comparator (Comp) Features. General Description. When to use a Comparator Low input offset. User controlled offset calibration
1.50 Features Low input offset User controlled offset calibration Multiple speed modes Low power mode Output routable to digital logic blocks or pins Selectable output polarity Configurable operation mode
THIS SPEC IS OBSOLETE
THIS SPEC IS OBSOLETE Spec No: 002-09373 Spec Title: AN209373 - F2MC-FM3 Family OpenOCD GUI Frontend Replaced by: 002-0586 AN209373 This application note describes how to use on-board Open On-Chip Debug
Setting Oscillation Stabilization Wait Time of the main clock (CLKMO) and sub clock (CLKSO)
1.0 Features Selecting Clock mode Internal Bus Clock Frequency Division Control PLL Clock Control Setting Oscillation Stabilization Wait Time of the main clock (CLKMO) and sub clock (CLKSO) Interrupts
CE CY8CKIT-042-BLE F-RAM Data Logger
CE210988 - CY8CKIT-042-BLE F-RAM Data Logger Objective This example project is based on a PSoC Creator starter design for the PSoC 4 device. It demonstrates how F-RAM can be used with the PSoC to capture
W H I T E P A P E R. Timing Uncertainty in High Performance Clock Distribution. Introduction
W H I T E P A P E R Brijesh A Shah, Cypress Semiconductor Corp. Timing Uncertainty in High Performance Clock Distribution Abstract Several factors contribute to the timing uncertainty when using fanout
4-word burst user selectable; dual bus master; SAR; SDR; same-cycle Read result Synchronous
Application Note Abstract Choosing The Right Cypress SRAM AN4011 Author: OSN Associated Project: None Associated Part Family: All Sync SRAMs Software Version: None Associated Application Notes: None AN4011
One 32-bit counter that can be free running or generate periodic interrupts
PSoC Creator Component Datasheet Multi-Counter Watchdog (MCWDT_PDL) 1.0 Features Configures up to three counters in a multi-counter watchdog (MCWDT) block Two 16-bit counters that can be free running,
THIS SPEC IS OBSOLETE
THIS SPEC IS OBSOLETE Spec Number: 001-84741 Spec Title: PSoC 5 to PSoC 5LP Migration Guide Sunset Owner: MKEA Replaced By: None AN84741 Author: Mark Ainsworth Associated Project: No Associated Part Family:
PSoC Creator Quick Start Guide
PSoC Creator Quick Start Guide Install Download PSoC Creator from www.cypress.com/psoccreator, or install from a kit CD. For assistance, go to http://www.cypress.com/go/support For features, system requirements,
CY8C29/27/24/23/21xxx, CY8CLED02/04/08/16, CY8CLED0xD, CY8CLED0xG, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28xxx. Main UM
Datasheet OneWire V 1.1 001-43362 Rev. *I OneWire Copyright 2008-2014 Cypress Semiconductor Corporation. All Rights Reserved. Resources PSoC Blocks API Memory (Bytes) Digital Analog CT Analog SC Flash
The AMuxSeq is capable of having between 2 and 32 analog inputs. The paired inputs are present when the MuxType parameter is set to "Differential.
1.20 Features Single or differential inputs Adjustable between 2 and 32 inputs Software controlled Inputs may be pins or internal sources No simultaneous connections Bidirectional (passive) General Description
Supports one or two address decoding with independent memory buffers. Memory buffers provide configurable Read/Write and Read Only regions
PSoC Creator Component Datasheet EZI2C Slave 1.70 Features Industry standard Philips I 2 C bus interface Emulates common I 2 C EEPROM interface Only two pins (SDA and SCL) required to interface to I 2
4-Mbit (512K x 8) Static RAM
4-Mbit (512K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive: 40 C to 125 C High speed t AA = 10 ns Low active power 324 mw (max.) 2.0V data retention