Preface... xxi Chapter One: Digital Signals and Systems... 1 Chapter Two: Numbering Systems... 17

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1 TABLE OF CONTENTS Preface...xxi Chapter One: Digital Signals and Systems Should Software Engineers Worry About Hardware? Non-Digital Signals Digital Signals Conversion Systems Representation of Digital Signals Types of Digital Signals Edges Pulses Non-Periodic Pulse Trains Periodic Pulse Trains Pulse-Width Modulation Unit Prefixes What's Next? Problems Chapter Two: Numbering Systems Unsigned Binary Counting Binary Terminology Unsigned Binary to Decimal Conversion Decimal to Unsigned Binary Conversion Binary Representation of Analog Values Sampling Theory Hexadecimal Representation Binary Coded Decimal Gray Codes What's Next? Problems Chapter Three: Binary Math and Signed Representations Binary Addition Binary Subtraction Binary Complements One's Complement Two's Complement Most Significant Bit as a Sign Indicator Signed Magnitude v

2 vi Computer Organization and Design Fundamentals MSB and Number of Bits Issues Surrounding the Conversion of Binary Numbers Minimums and Maximums Floating Point Binary Hexadecimal Addition BCD Addition Multiplication and Division by Powers of Two Easy Decimal to Binary Conversion Trick Arithmetic Overflow What's Next? Problems Chapter Four: Logic Functions and Gates Logic Gate Basics NOT Gate AND Gate OR Gate Exclusive-OR (XOR) Gate Truth Tables Timing Diagrams for Gates Combinational Logic Truth Tables for Combinational Logic What's Next? Problems Chapter Five: Boolean Algebra Need for Boolean Expressions Symbols of Boolean Algebra Boolean Expressions of Combinational Logic Laws of Boolean Algebra Rules of Boolean Algebra NOT Rule OR Rules AND Rules XOR Rules Derivation of Other Rules Simplification DeMorgan's Theorem What's Next? Problems

3 Table of Contents vii Chapter Six: Standard Boolean Expression Formats Sum-of-Products Converting an SOP Expression to a Truth Table Converting a Truth Table to an SOP Expression Product-of-Sums Converting POS to Truth Table Converting a Truth Table to a POS Expression NAND-NAND Logic What's Next? Problems Chapter Seven: Karnaugh Maps The Karnaugh Map Using Karnaugh Maps "Don't Care" Conditions in a Karnaugh Map What's Next? Problems Chapter Eight: Combinational Logic Applications Adders Seven-Segment Displays Active-Low Signals Decoders Multiplexers Demultiplexers Integrated Circuits What's Next? Problems Chapter Nine: Binary Operation Applications Bitwise Operations Clearing/Masking Bits Setting Bits Toggling Bits Comparing Bits with XOR Parity Checksum Cyclic Redundancy Check CRC Process CRC Implementation Hamming Code

4 viii Computer Organization and Design Fundamentals 9.7 What's Next? Problems Chapter Ten: Memory Cells New Truth Table Symbols Edges/Transitions Previously Stored Values Undefined Values The S-R Latch The D Latch Divide-By-Two Circuit Counter Parallel Data Output What's Next? Problems Chapter Eleven: State Machines Introduction to State Machines States State Diagrams Errors in State Diagrams Basic Circuit Organization State Machine Design Process Another State Machine Design: Pattern Detection Mealy Versus Moore State Machines What's Next? Problems Chapter Twelve: Memory Organization Early Memory Organization of Memory Device Interfacing Memory to a Processor Buses Memory Maps Address Decoding Chip Select Hardware Memory Mapped Input/Output Memory Terminology Random Access Memory Read Only Memory Static RAM versus Dynamic RAM

5 Table of Contents ix Types of DRAM and Their Timing Asynchronous vs. Synchronous Memory What's Next? Problems Chapter Thirteen: Memory Hierarchy Characteristics of the Memory Hierarchy Physical Characteristics of a Hard Drive Hard Drive Read/Write Head Data Encoding Hard Drive Access Time S.M.A.R.T Organization of Data on a Hard Drive Cache RAM Cache Organization Dividing Memory into Blocks Cache Operation Cache Characteristics Cache Mapping Functions Cache Write Policy Registers What's Next? Problems Chapter Fourteen: Serial Protocol Basics OSI Seven-Layer Network Model Serial versus Parallel Data Transmission Anatomy of a Frame or Packet Sample Protocol: IEEE Ethernet Sample Protocol: Internet Protocol Sample Protocol: Transmission Control Protocol Dissecting a Frame Additional Resources What's Next? Problems Chapter Fifteen: Introduction to Processor Architecture Organization versus Architecture Components Bus Registers

6 x Computer Organization and Design Fundamentals Flags Buffers The Stack I/O Ports Processor Level CPU Level Simple Example of CPU Operation Assembly and Machine Language Big-Endian/Little-Endian Pipelined Architectures Passing Data To and From Peripherals Memory-Mapped I/O Polling Interrupts Direct Memory Access I/O Channels and Processors What's Next? Problems Chapter Sixteen: Intel 80x86 Base Architecture Why Study the 80x86? Execution Unit General Purpose Registers Address Registers Flags Internal Buses Bus Interface Unit Segment Addressing Instruction Queue Memory versus I/O Ports What's Next? Problems Chapter Seventeen: Intel 80x86 Assembly Language Assemblers versus Compilers Components of a Line of Assembly Language Assembly Language Directives SEGMENT Directive MODEL,.STACK,.DATA, and.code Directives PROC Directive

7 Table of Contents xi END Directive Data Definition Directives EQU Directive x86 Opcodes Data Transfer Data Manipulation Program Control Special Operations Addressing Modes Register Addressing Immediate Addressing Pointer Addressing Sample 80x86 Assembly Language Programs Additional 80x86 Programming Resources What's Next? Problems Index TABLE OF FIGURES 1-1 Sample Digital System Continuous Analog Signal with Infinite Resolution Sample of Discrete Measurements Taken Every 0.1 Sec Samples Taken of an Analog Signal Slow Sampling Rate Missed an Anomaly Poor Resolution Resulting in an Inaccurate Measurement Block Diagram of a System to Capture Analog Data Representation of a Single Binary Signal Representation of Multiple Digital Signals Alternate Representation of Multiple Digital Signals Digital Transition Definitions Pulse Waveforms Non-Periodic Pulse Train Periodic Pulse Train Periodic Pulse Train with Different Pulse Widths Periodic Pulse Train with 25% Duty Cycle Counting in Decimal... 17

8 xii Computer Organization and Design Fundamentals 2-2 Counting in Binary Binary-Decimal Equivalents from 0 to Values Represented By Each of the First 8 Bit Positions Sample Conversion of to Decimal Decimal to Unsigned Binary Conversion Flow Chart Sample Analog Signal of Sound Effects of Number of Bits on Roundoff Error Aliasing Effects Due to Slow Sampling Rate Eight Binary Values Identifying Rotating Shaft Position Example of a Position Encoder Conversion from Unsigned Binary to Gray Code Four Possible Results of Adding Two Bits Four Possible Results of Adding Two Bits with Carry Two's Complement Short-Cut Converting a Two's Complement Number to a Decimal IEEE Standard 754 Floating-Point Formats Duplicate MSB for Right Shift of 2's Complement Values Basic Format of a Logic Gate Basic Logic Symbols Operation of the NOT Gate Operation of a Two-Input AND Gate Operation of a Two-Input OR Gate Operation of a Two-Input XOR Gate Sample Three-Input Truth Table Listing All Bit Patterns for a Four-Input Truth Table Inverter Truth Table Two-Input AND Gate Truth Table Two-Input OR Gate Truth Table Two-Input XOR Gate Truth Table Three-Input AND Gate Truth Table With Don't Cares Sample Timing Diagram for a Three-Input AND Gate Sample Timing Diagram for a Three-Input OR Gate Sample Timing Diagram for a Three-Input XOR Gate Sample Combinational Logic Combinational Logic for a Simple Security System Truth Table for Simple Security System of Figure "NOT" Circuits Schematic "Short-Hand" for Inverted Inputs... 82

9 Table of Contents xiii 4-22 Sample of Multi-Level Combinational Logic Process of Passing Inputs Through Combinational Logic Steps That Inputs Pass Through in Combinational Logic All Combinations of Ones and Zeros for Three Inputs Step (a) in Sample Truth Table Creation Step (b) in Sample Truth Table Creation Step (c) in Sample Truth Table Creation Step (d) in Sample Truth Table Creation Schematic and Truth Table of Combinational Logic Boolean Expression for the AND Function Boolean Expression for the OR Function Boolean Expression for the NOT Function Circuit Representation of the Boolean Expression Sample of Multi-Level Combinational Logic Creating Boolean Expression from Combinational Logic Examples of the Precedence of the NOT Function Example of a Conversion from a Boolean Expression Commutative Law for Two Variables OR'ed Together Schematic Form of NOT Rule Rules of Boolean Algebra Application of DeMorgan's Theorem Schematic Application of DeMorgan's Theorem Sample Sum-of-Products Binary Circuit Samples of Single Product (AND) Truth Tables Sample of a Sum-of-Products Truth Table Conversion of an SOP Expression to a Truth Table Sample Product-of-Sums Binary Circuit Samples of Single Sum (OR) Truth Tables Sample of a Product-of-Sums Truth Table Sample Sums With Multiple Zero Outputs Conversion of a POS Expression to a Truth Table Circuit Depiction of DeMorgan's Theorem OR Gate Equals a NAND Gate With Inverted Inputs OR-to-NAND Equivalency Expanded to Four Inputs Sample SOP Circuit Sample SOP Circuit with Output OR Gate Replaced Sample SOP Circuit Implemented With NAND Gates by-2 Karnaugh Map Used with Two Inputs

10 xiv Computer Organization and Design Fundamentals 7-2 Mapping a 2-Input Truth Table to Its Karnaugh Map Three-Input Karnaugh Map Four-Input Karnaugh Map Identifying the Products in a Karnaugh Map Karnaugh Map with Four Adjacent Cells Containing '1' Sample Rectangle in a Three-Input Karnaugh Map Karnaugh Map with a "Don't Care" Elements Karnaugh Map with a "Don't Care" Elements Assigned Four Possible Results of Adding Two Bits Block Diagram of a Half Adder Four Possible States of a Half Adder Logic Circuit for a Half Adder Block Diagram of a Multi-bit Adder Block Diagram of a Full Adder Sum and Carryout Karnaugh Maps for a Full Adder Logic Circuit for a Full Adder Seven-Segment Display Displaying a '1' with a 7-Segment Display A Seven-Segment Display Displaying a Decimal '2' Block Diagram of a Seven-Segment Display Driver Segment Patterns for all Hexadecimal Digits Seven Segment Display Truth Table Karnaugh Map for Segment 'e' Karnaugh Map for Segment 'e' with Rectangles Logic Circuit for Segment e of 7-Segment Display Labeling Conventions for Active-Low Signals Sample Circuit for Enabling a Microwave Sample Circuit for Delivering a Soda Truth Table to Enable a Device for A=1, B=1, & C= Digital Circuit for a 1-of-4 Decoder Digital Circuit for an Active-Low 1-of-4 Decoder Truth Table for an Active-Low 1-of-8 Decoder Block Diagram of an Eight Channel Multiplexer Truth Table for an Eight Channel Multiplexer Logic Circuit for a 1-Line-to-4-Line Demultiplexer Truth Table for a 1-Line-to-4-Line Demultiplexer Examples of Integrated Circuits Pin-out of a Quad Dual-Input NAND Gate IC (7400) Sample Pin 1 Identifications

11 Table of Contents xv 8-32 Generic Protoboard Generic Protoboard Internal Connections Sample Circuit Wired on a Protoboard Schematic Symbol of a Light-Emitting Diode (LED) LED Circuit Switch Circuit Graphic of a Bitwise Operation Performed on LSB Bitwise AND of and Three Sample Bitwise ANDs Possible Output from a Motion Detector A Difference in Output Indicates an Error Simple Error Detection with an XOR Gate Sample Block of Data with Accompanying Datasums Small Changes in Data Canceling in Checksum Example of Long Division in Binary Example of Long Division Using XOR Subtraction Sample Code for Calculating CRC Checksums Venn Diagram Representation of Hamming Code Example Single-Bit Errors in Venn Diagram Example of a Two-Bit Error Using Parity to Check for Double-Bit Errors Symbols for Rising Edge and Falling Edge Transitions Sample Truth Table Using Undefined Output Primitive Feedback Circuit using Inverters Operation of a NAND Gate with One Input Tied High Primitive Feedback Circuit Redrawn with NAND Gates Only Two Possible States of Circuit in Figure Operation of a Simple Memory Cell Operation of a Simple Memory Cell (continued) S-R Latch S-R Latch Truth Table Block Diagram of the D Latch Edge-Triggered D Latch Truth Tables Transparent D Latch Truth Tables Divide-By-Two Circuit Clock and Output Timing in a Divide-By-Two Circuit Cascading Four Divide-By-Two Circuits Counter Implemented with Divide-By-Two Circuits

12 xvi Computer Organization and Design Fundamentals Output of Binary Counter Circuit Output Port Data Latch Circuitry Adding Memory to a Digital Logic Circuit States of a Traffic Signal System States of a Light Bulb State Diagram for Light Bulb State Machine Complete State Diagram for Light Bulb State Machine Block Diagram of an Up-Down Binary Counter State Diagram for a 3-Bit Up-Down Binary Counter Sample of a Reset Indication in a State Diagram Block Diagram of a State Machine Initial State of the Push Button Light Control Transitions from State 0 of Push Button Circuit B=0 Transition from State 0 of Push Button Circuit B=1 Transition from State 0 of Push Button Circuit B=0 Transition from State 1 of Push Button Circuit B=1 Transition from State 1 of Push Button Circuit Transitions from State 2 of Push Button Circuit Final State Diagram for Push Button Circuit Block Diagram for Push Button Circuit K-Maps for S 1 ', S 0 ', and L of Push Button Circuit Finished Push Button Circuit Revised Truth Table and K Map for Push Button Circuit Identifying the Bit Pattern "101" in a Bit Stream State Diagram for Identifying the Bit Pattern "101" Next State and Output Truth Tables for Pattern Detect K-Maps for S 1 ', S 0 ', and P of Pattern Detect Circuit Final Circuit to Identify the Bit Pattern "101" Basic Configuration of a Mealy Machine Sample State Diagram of a Mealy Machine Output Truth Table for Sample Mealy Machine Diagram of a Section of Core Memory Basic Organization of a Memory Device Basic Processor to Memory Device Interface Two Memory Devices Sharing a Bus Three Buffers Trying to Drive the Same Output Sample Memory Maps Full Address with Enable Bits and Device Address Bits

13 Table of Contents xvii 12-8 IPv4 Address Divided into Subnet and Host IDs Sample Chip Select Circuit for a Memory Device Some Types of Memory Mapped I/O Configurations Basic Addressing Process for a DRAM Organization of DRAM Example of an FPM Transfer Example of an EDO Transfer Block Diagram of a Standard Memory Hierarchy Configuration of a Hard Drive Write Head Sample FM Magnetic Encoding Sample MFM Magnetic Encoding RLL Relation between Bit Patterns and Polarity Changes Sample RLL Magnetic Encoding Components of Disk Access Time Relation between Read/Write Head and Tracks Organization of Hard Disk Platter Illustration of a Hard Drive Cylinder Equal Number of Bits per Track versus Equal Sized Bits Comparison of Sector Organizations Cache Placement between Main Memory and Processor L1 and L2 Cache Placement Split Cache Organization Organization of Cache into Lines Division of Memory into Blocks Organization of Address Identifying Block and Offset Direct Mapping of Main Memory to Cache Direct Mapping Partitioning of Memory Address Fully Associative Partitioning of Memory Address Set Associative Mapping of Main Memory to Cache Effect of Cache Set Size on Address Partitioning Sample Protocol Stack using TCP, IP, and Ethernet Layout of an IEEE Ethernet Frame Layout of an IP Packet Header Layout of a TCP Packet Header Position and Purpose of TCP Control Flags Layout of a TCP Pseudo Header Simulated Raw Data Capture of an Ethernet Frame Sample Code Using Conditional Statements

14 xviii Computer Organization and Design Fundamentals 15-2 Block Diagram of a System Incorporating a Buffer Generic Block Diagram of a Processor System Generic Block Diagram of Processor Internals Generic Block Diagram of a Typical CPU Decoded Assembly Language from Table Non-Pipelined Execution of Five Instructions Pipelined Execution of Five Instructions Sample Memory Mapped Device Circuit Basic Operation of an ISR Block Diagram of 80x86 Execution Unit (EU) Block Diagram of 80x86 Bus Interface Unit (BIU) Segment/Pointer Relation in the 80x86 Memory Map Format of a Line of Assembly Language Code Format and Parameters Used to Define a Segment Format of the.model Directive Format and Parameters Used to Define a Procedure Format and Parameters of Some Define Directives Example Uses of Define Directives Format and Parameters of the EQU Directive Sample Code with and without the EQU Directive Format and Parameters of the MOV Opcode Format and Parameters of the IN and OUT Opcodes Format and Parameters of the ADD Opcode Format and Parameters of NEG, NOT, DEC, and INC Format and Parameters of SAR, SHR, SAL, and SHL Example of a JMP Instruction Example of a LOOP Instruction Sample Organization of a Procedure Call Examples of Register Addressing Examples of Immediate Addressing Examples of an Address being used as an Operand Skeleton Code for a Simple Assembly Program Code to Assign Data Segment Address to DS Register Code to Inform O/S that Program is Terminated Skeleton Code with Code Added for O/S Support Data Defining Directives for Example Code Step-by-Step Example Operation Converted to Code Final Code for Example Assembly Language Program

15 Table of Contents xix TABLE OF TABLES 1-1 Unit Prefixes Converting Binary to Decimal and Hexadecimal Converting BCD to Decimal Derivation of the Four-Bit Gray Code Representation Comparison for 8-bit Binary Numbers Hexadecimal to Decimal Conversion Table Multiplying the Binary Value by Powers of Two Addition Results Based on Inputs of a Full Adder Sum and Carryout Truth Tables for a Full Adder Truth Table for a Two-Input XOR Gate Addition and Subtraction Without Carries or Borrows Reconstructing the Dividend Using XORs Second Example of Reconstructing the Dividend Data Groupings and Parity for the Nibble Data Groupings with a Data Bit in Error Data Groupings with a Parity Bit in Error Identifying Errors in a Nibble with Three Parity Bits Parity Bits Required for a Specific Number of Data Bits Membership of Data and Parity Bits in Parity Groups List of States for Push Button Circuit Next State Truth Table for Push Button Circuit Output Truth Table for Push Button Circuit Revised List of States for Push Button Circuit List of States for Bit Pattern Detection Circuit The Allowable Settings of Four Chip Selects Sample Memory Sizes versus Required Address Lines Conditional Jumps to be Placed After a Compare Conditional Jumps to be Placed After an Operation Numbered Instructions for Imaginary Processor Assembly Language for Imaginary Processor Operand Requirements for Imaginary Processor A Simple Program Stored at Memory Address Signal Values for Sample I/O Device Control Signal Levels for I/O and Memory Transactions

16 xx Computer Organization and Design Fundamentals 16-1 Summary of Intel 80x86 Bus Characteristics Summary of the 80x86 Read and Write Control Signals Memory Models Available for use with.model Summary of 80x86 Conditional Jumps x86 Instructions for Modifying Flags

INDEX. asynchronous memory, 270 auxiliary carry flag, 366 AX. See accumulator register

INDEX. asynchronous memory, 270 auxiliary carry flag, 366 AX. See accumulator register A accumulator register, 363 accuracy, 6 active-low signals, 153, 253 address decoder, 249 address decoding, 257 address latch, 335 address lines, 251 address, memory, 248 addressing immediate, 384 pointer,