Sub Name: Computer Architecture and Organization. UNIT-IV-Memory Organization

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1 Sub Code:EC2303 Dept: ECE Sub Name: Computer Architecture and Organization UNIT-IV-Memory Organization 1. Give the features of a ROM cell (AUC APR 08) Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware. ROM refers only to mask ROM,which is fabricated with the desired data permanently stored in it, and thus can never be modified. Despite the simplicity, speed and economies of scale of mask ROM, field-programmability often make reprogrammable memories more flexible and inexpensive 2.List the differences between static RAM and dynamic RAM.(AUC APR 11 08) SRAM is static while DRAM is dynamic. SRAM is faster compared to DRAM SRAM consumes less power than DRAM SRAM uses more transistors per bit of memory compared to DRAM SRAM is more expensive than DRAM Cheaper DRAM is used in main memory while SRAM is commonly used in cache memory 3. Define Locality of Reference. (AUC NOV 09,MAY 08) The tendency of a process to access the same set of memory locations repetitively over a short period of time Two types temporal and locality reference, 4. What is Translation Look aside Buffer? (AUCMAY 06) The translation look aside buffer (TLB) is a cache for page table entries. It works in much the same way as the data cache: it stores recently accessed page table entries. It also relies on locality of reference. Since each TLB entry covers a whole page of physical memory (512-8Kbytes, commonly 4Kbytes), a relatively small number of TLB entries will cover a large amount of program memory. 5. Define memory access time. The time required by a processor to access data or to write data from and to memory chip is referred as access time. 6. Define Cache memory. Memory word are stored in cache data memory and are grouped into small pages called cache blocks or line. The contents of the cache s data memory are thus copies of a set of main memory blocks. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 1

2 7. Define Virtual Memory. virtual memory is a memory management technique that is implemented using both hardware and software. It maps memory addresses used by a program, called virtual addresses, into physical addresses in computer memory. Main storage as seen by a process or task appears as a contiguous address space or collection of contiguous segments. The operating system manages virtual address spaces and the assignment of real memory to virtual memory. 8. What is meant by internal and external fragmentation?(auc APR 11) External Fragmentation: External Fragmentation happens when a dynamic memory allocation algorithm allocates some memory and a small piece is left over that cannot be effectively used. If too much external fragmentation occurs, the amount of usable memory is drastically reduced. Total memory space exists to satisfy a request, but it is not contiguous. Internal Fragmentation: Internal fragmentation is the space wasted inside of allocated memory blocks because of restriction on the allowed sizes of allocated blocks. Allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used. 9. Define Synchronous DRAMS. Synchronous dynamic random access memory (SDRAM) is dynamic random access memory (DRAM) with an interface synchronous with the system bus carrying data between the CPU and the memory controller hub. SDRAM has a rapidly responding synchronous interface, which is in sync with the system bus. SDRAM waits for the clock signal before it responds to control input 10. What is Random Access Memory (RAM)?(AUC MAY 2013) In storage location can be accessed in any order and access time is independent of the location being accessed, the memory is termed as random access memory. 11. What is the use of virtual memory?(auc MAY 12 13) Protection: VM is often used to protect one program from others in the system Base and Bounds: this method allows relocation. User processes cannot be allowed to change these registers, but the OS must be able to do so on a process switch. 12. What is PROM? Semi conductor ROMs whose contents can be changed offline-with some difficulties is called PROMs. 13. What is EPROM? EPROM (Erasable Programmable Read Only Memory) EPROM did not allow the data to be changed. That is the reason why it gained popularity pretty quickly among hardware makers and hobbyists. EPROMS allow them to fully deploy their A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 2

3 program on the chip then test it, once bugs are found they can erase the EPROM then load a modified version for further testing. 14. What is EEPROM? Electrically Erasable Programmable memory. The only difference between the two is that you can erase an EEPROM with electricity EEPROM also allowed manufacturers to release patches if the program. 15. Draw the structure of Memory hierarchy. CPU Levels in the memory hierarchy Level 1 Level 2 Increasing distance from the CPU in access time Level n Size of the memory at each level 16. What is write-through protocol? write operation,the cache location and the main memory location are updated simultaneously. 17. What is write-back (or) copy-back protocol? In this scheme, only the block in cache is modified. The main memory when the block must be replaces in the cache. This requires the use of a dirty bit to keep track of blocks, that have been modified 18. What is RAMBUS memory? The key feature of Rambus technology is a fast signaling method used to transfer information between chip using narrow bus 19. Mention two system organization for caches. Two system organization for caches are a. look aside b. look through 20. What are the categories of memories? SRAM DRAM A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 3

4 21. What is flash memor?. A recent semiconductor technology called flash memory of a same non-volatility as a PROM, but it can be done a bit at a time. 22.What is SRAM AND DRAM? SRAM:Static randam access memory. It tends to be faster.they require no refreshing DRAM:Dynamic random access memory. Data is stored in the form of charges. So continuous refreshing is needed. 23. What is volatile memory? A memory is volatile if the loss of power destroys the stored information. Information can be stored indefinitely in a volatile memory by providing battery backup or other means to maintain a continuous supply of power. 24.Give the difference between EEPROM and Flash memory? The primary difference between EEPROM and flash memory is that flash restricts writes to multiple kilobytes blocks, increasing the memory capacity per chip by reducing area of control. 25. Differences between cache memory and virtual memery 1. In caches, replacement is primarily controlled by the hardware. In VM, replacement is primarily controlled by the os. 2. The Number of bits in the address determines the size of VM, where as cache size is independent of the address size. But there is only one class of cache. PART B 1. Describe the organization of a typical RAM chip. ( AUC MAY 07,) Random-access memory, or RAM, provides large quantities of temporary storage in a computer system. Remember the basic capabilities of a memory: It should be able to store a value. read the value that was saved. change the stored value. A RAM is similar, except that it can store many values. An address will specify which memory value we re interested in. Each value can be a multiple-bit word A Chip Select, CS, enables or disables the RAM. ADRS specifies the address or location to read from or write to. WR selects between reading from or writing to the memory. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 4

5 To read from memory, WR should be set to 0. OUT will be the n-bit value stored at ADRS. To write to memory, we set WR = 1. DATA is the n-bit value to save in memory. This interface makes it easy to combine RAMs together, 2k x n memory. There are k address lines, which can specify one of 2k addresses. Each address contains an n-bit word. o For example, a 224 x 16 RAM contains 224 = 16M words, each 16 bits long. The RAM would need 24 address lines. The total storage capacity is 224 x 16 = 228 bits. To read from this RAM, the controlling circuit must: Enable the chip by ensuring CS = 1. Select the read operation, by setting WR = 0. Send the desired address to the ADRS input. The contents of that address appear on OUT after a little while. Static memory is modeled using one latch for each bit of storage. A latch can be made with only two NAND or two NOR gates, but a flip-flop requires at least twice that much hardware. smaller is faster, cheaper and requires less power..the tradeoff is that getting the timing exactly right is a pain. these cells to make a 4 x 1 RAM. Since there are four words, ADRS is two bits. Each word is only one bit, so DATA and OUT are one bit each. Word selection is done with a decoder attached to the CS inputs of the RAM cells. Only one cell can be read or written at a time. Notice that the outputs are connected together with a single line! A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 5

6 If the decoder is disabled, then all the three-state buffers will appear to be disconnected, and OUT will also appear disconnected. If the decoder is enabled, then exactly one of its outputs will be true, so only one of the tristate buffers will be connected and produce an output. The net result is we can save some wire and gate costs. little more flexibility in putting circuits together. DATA and OUT are now each four bits long, so you can read and write four-bit words 2. Explain about Cache memory in detail. (AUC NOV 06,APR 08 MAY 13) Cache Memories Speed of the main memory is very low in comparison with the speed of processor A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 6

7 For good performance, the processor cannot spend much time of its time waiting to access instructions and data in main memory. Important to device a scheme that reduces the time to access the information An efficient solution is to use fast cache memory When a cache is full and a memory word that is not in the cache is referenced, the cache control hardware must decide which block should be removed to create space for the new block that contain the referenced word. The basics of Caches " The caches are organized on basis of blocks, the smallest amount of data which can be copied between two adjacent levels at a time. " If data requested by the processor is present in some block in the upper level, it is called a hit. " If data is not found in the upper level, the request is called a miss and the data is retrieved from the lower level in the hierarchy. " The fraction of memory accesses found in the upper level is called a hit ratio. " The storage, which takes advantage of locality of accesses is called a cache A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 7

8 Performance of caches Accessing a Cache Address Mapping in Cache: Direct Mapping In this technique, block j of the main memory maps onto block j modulo 128 of the cache. Main memory blocks 0,128,256, is loaded in the cache, it is stored in cache block 0. Blocks 1,129,257, are stored in cache block 1. Direct mapped cache A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 8

9 Associative Mapping More flexible mapping technique A main memory block can be placed in to any cache block position. Space in the cache can be used more efficiently, but need to search all 128 tag patterns. Set-Associate Mapping Combination of the direct- and associative mapping technique Blocks of the cache are grouped into sets, and the mapping allows a block of the A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 9

10 Main memory to reside in any block of a specific set. Note: Memory blocks 0,64,128,,4032 maps into cache set 0. Calculating Block Size: Write hit policies. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 10

11 REPLACEMENT POLICY: On a cache miss we need to evict a line to make room for the new line " In an A-way set associative cache,! least-recently used (true LRU is too costly)! pseudo LRU (Approximated LRU - in case of four-way set associativity one bit keeps track of which pair of blocks is LRU, and then tracking which block in each pair is LRU (one bit per pair))! fixed (processing audio stream) For a two-way set associative cache, random replacement has a miss rate about o time higher than LRU replacement. As the caches become larger, the miss rate for both replacement strategies fall, and the difference becomes small. Random replacement is sometimes better than simple LRU approximations that can be easily implemented in hardware. WRITE MISS POLICY: Write allocate allocate a new block on each write fetch on write fetch entire block, then write word into block no-fetch- allocate block, but don t fetch requires valid bits per word more complex eviction Write no-allocate don t allocate a block if it is not already in the cache write around the cache typically used by write through since we need update main memory anyway Write invalidate instead of update for write-through Measuring and Improving Cache Performance A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 11

12 2.Explain the concept of memory hierarchy(aucnov 07 06) Principle of Locality: Program access a relatively small portion of the address space at any instant of time 90/10 rule: 10% of code executed 90% of time Two types of locality: Temporal locality: if an item is referenced, it will tend to be referenced again soon Spatial locality: if an item is referenced, items whose addresses are close by tend to be referenced soon Random access: Access time same for all locations DRAM: Dynamic Random Access Memory High density, low power, cheap, slow Dynamic: need to be refreshed regularly Addresses in 2 halves (memory as a 2D matrix): RAS/CAS (Row/Column Access Strobe) Use for main memory SRAM: Static Random Access Memory Low density, high power, expensive, fast Static: content will last (forever until lose power) Address not divided A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 12

13 Usefor caches Hit: data appears in upper level (Block X) Hit rate: fraction of memory access found in the upper level Hit time: time to access the upper level RAM access time + Time to determine hit/miss Miss: data needs to be retrieved from a block in the lower level (Block Y) Miss Rate = 1 - (Hit Rate) o Miss Penalty: time to replace a block in the upper level + time to deliver the block to the processor (latency + transmit time) o Hit Time << Miss Penalty 3. Describe the working principle of a typical magnetic disk.(auc APR 08,MAY 13) Magnetic disks provide bulk of secondary storage of modern computers Drives rotate at 60 to 200 times per second Transfer rate is rate at which data flow between drive and computer Positioning time (random-access time) is time to move disk arm to desired cylinder (seek time) and time for desired sector to rotate under the disk head (rotational latency) o Head crash results from disk head making contact with the disk surface Disks can be removable Drive attached to computer via I/O bus Busses vary, including EIDE, ATA, SATA, USB, Fibre Channel, SCSI A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 13

14 Host controller in computer uses bus to talk to disk controller built into drive or storage array Disk drives are addressed as large 1-dimensional arrays of logical blocks, where the logical block is the smallest unit of transfer. The 1-dimensional array of logical blocks is mapped into the sectors of the disk sequentially. Sector 0 is the first sector of the first track on the outermost cylinder. Mapping proceeds in order through that track, then the rest of the tracks in that cylinder, and then through the rest of the cylinders from outermost to innermost. Host-attached storage accessed through I/O ports talking to I/O busses SCSI itself is a bus, up to 16 devices on one cable, SCSI initiator requests operation and SCSI targets perform tasks.each target can have up to 8 logical units (disks attached to device controller FC is high-speed serial architecture Can be switched fabric with 24-bit address space the basis of storage area networks (SANs) in which many hosts attach to many storage units Can be arbitrated loop (FC-AL) of 126 devices Network-attached storage (NAS) is storage made available over a network rather than over a local connection (such as a bus) NFS and CIFS are common protocols. Implemented via remote procedure calls (RPCs) between host and storage New iscsi protocol uses IP network to carry the SCSI protocol A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 14

15 Disk scheduling: The operating system is responsible for using hardware efficiently for the disk drives, this means having a fast access time and disk bandwidth. Access time has two major components Seek time is the time for the disk are to move the heads to the cylinder containing the desired sector. Rotational latency is the additional time waiting for the disk torotate the desired sector to the disk head. Minimize seek time Seek time seek distance Disk bandwidth is the total number of bytes transferred, divided by the total time between the first request for service and thecompletion of the last transfer 4. How a virtual address gets translated into a physical address? Explain in detail with a neat diagram. Explain the use of TLB. (AUCAPR 08, NOV 06) What is virtual memory? How is it implemented? (AUCNOV 07,06,08) Virtual memory is a computer system technique which gives an application program the impression that it has contiguous working memory (an address space), while in fact it may be physically fragmented and may even overflow on to disk storage. Virtual memory provides two primary functions: 1. Each process has its own address space, thereby not required to be relocated nor required to use relative addressing mode. 2. Each process sees one contiguous block of free memory upon launch. Fragmentation is hidden. All implementations (Excluding emulators) require hardware support. This is typically in the form of a Memory Management Unit built into the CPU. Systems that use this technique make programming of large applications easier and use real physical memory (e.g. RAM) more efficiently than those without virtual memory. Virtual memory differs significantly from memory virtualization in that virtual memory allows resources to be virtualized as memory for a specific system, as opposed to a large pool of memory being virtualized as smaller pools for many different systems. Note that "virtual memory" is more than just "using disk space to extend physical memory size" - that is merely the extension of the memory hierarchy to include hard disk drives. Extending memory to disk is a normal consequence of using virtual memory techniques, but could be done by other means such as overlays or swapping programs and their data completely out to disk while they are inactive. The definition of "virtual memory" is based on redefining the address space with a contiguous virtual memory addresses to "trick" programs into thinking they are using large blocks of contiguous addresses. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 15

16 Paged virtual memory Almost all implementations of virtual memory divide the virtual address space of an application program into pages; a page is a block of contiguous virtual memory addresses. Pages are usually at least 4K bytes in size, and systems with large virtual address ranges or large amounts of real memory (e.g. RAM) generally use larger page sizes. Page tables Almost all implementations use page tables to translate the virtual addresses seen by the application program into physical addresses (also referred to as "real addresses") used by the hardware to process instructions. Each entry in the page table contains a mapping for a virtual page to either the real memory address at which the page is stored, or an indicator that the page is currently held in a disk file. (Although most do, some systems may not support use of a disk file for virtual memory.) Systems can have one page table for the whole system or a separate page table for each application. If there is only one, different applications which are running at the same time share a single virtual address space, i.e. they use different parts of a single range of virtual addresses. Systems which use multiple page tables provide multiple virtual address spaces - concurrent applications think they are using the same range of virtual addresses, but their separate page tables redirect to different real addresses. Dynamic address translation while executing an instruction, a CPU fetches an instruction located at a particular virtual address, or fetches data from a specific virtual address or stores data to a particular virtual address, the virtual address must be translated to the corresponding physical address. This is done by a hardware component, sometimes called a memory management unit, which looks up the real address (from the page table) corresponding to a virtual address and passes the real address to the parts of the CPU which execute instructions. Paging supervisor This part of the operating system creates and manages the page tables. If the dynamic address translation hardware raises a page fault exception, the paging supervisor searches the page space on secondary storage for the page containing the required virtual address, reads it into real physical memory, updates the page tables to reflect the new location of the virtual address and finally tells the dynamic address translation mechanism to start the search again. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 16

17 Usually all of the real physical memory is already in use and the paging supervisor must first save an area of real physical memory to disk and update the page table to say that the associated virtual addresses are no longer in real physical memory but saved on disk. Paging supervisors generally save and overwrite areas of real physical memory which have been least recently used, because these are probably the areas which are used least often. So every time the dynamic address translation hardware matches a virtual address with a real physical memory address, it must put a time-stamp in the page table entry for that virtual address. Permanently resident pages All virtual memory systems have memory areas that are "pinned down", i.e. cannot be swapped out to secondary storage, for example: Interrupt mechanisms generally rely on an array of pointers to the handlers for various types of interrupt (I/O completion, timer event, program error, page fault, etc.). If the pages containing these pointers or the code that they invoke were pageable, interrupt-handling would become even more complex and time-consuming; and it would be especially difficult in the case of page fault interrupts. The page tables are usually not pageable. Data buffers that are accessed outside of the CPU, for example by peripheral devices that use direct memory access (DMA) or by I/O channels. Usually such devices and the buses (connection paths) to which they are attached use physical memory addresses rather than virtual memory addresses. Even on buses with an IOMMU, which is a special memory management unit that can translate virtual addresses used on an I/O bus to physical addresses, the transfer cannot be stopped if a page fault occurs and then restarted when the page fault has been processed. So pages containing locations to which or from which a peripheral device is transferring data are either permanently pinned down or pinned down while the transfer is in progress. Timing-dependent kernel/application areas cannot tolerate the varying response time caused by paging. complex and time-consuming; and it would be especially difficult in the case of page fault interrupts. The page tables are usually not pageable. Data buffers that are accessed outside of the CPU, for example by peripheral devices that use direct memory access (DMA) or by I/O channels. Usually such devices and the buses (connection paths) to which they are attached use physical memory addresses rather than virtual memory addresses. Even on buses with an IOMMU, which is a special memory management unit that can translate virtual addresses used on an I/O bus to physical addresses, the transfer cannot be stopped if a page fault occurs and then restarted when the page fault has been processed. So pages containing locations to which or from which a peripheral device is transferring data are either permanently pinned down or pinned down while the transfer is in progress. Timing-dependent kernel/application areas cannot tolerate the varying response time caused by paging. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 17

18 Compiler time: If it is known in advance that a program will reside at a specific location of main memory, then the compiler may be told to build the object code with absolute addresses right away. For example, the boot sect in a bootable disk may be compiled with the starting point of code set to 007C:0000. Load time: It is pretty rare that we know the location a program will be assigned ahead of its execution. In most cases, the compiler must generate relocatable code with logical addresses. Thus the address translation may be performed on the code during load time. Figure 3 shows that a program is loaded at location x. If the whole program resides on a monolithic block, then every memory reference may be translated to be physical by added to x. However two disadvantages are A program that is too big to be held in a partition needs some special design, called overlay, which brings heavy burden on programmers. With overlay, a process consists of several portions with each being mapped to the same location of the partition, and A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 18

19 at any time, only one portion may reside in the partition. When another portion is referenced, the current portion will be switched out. A program may be much smaller than a partition, thus space left in the partition will be wasted, which is referred to as internal fragmentation. As an improvement shown in Figure 4 (b), unequal-size partitions may be configured in main memory so that small programs will occupy small partitions and big programs are also likely to be able to fit into big partitions. Although this may solve the above problems with fixed 5 equal-size partitioning to some degree, the fundamental weakness still exists: The number of partitions are the maximum of the number of processes that could reside in main memory at the same time. When most processes are small, the system should be able to accommodate more of them but fails to do so due to the limitation. More flexibility is needed. Dynamic partitioning To overcome difficulties with fixed partitioning, partitioning may be done dynamically, called dynamic partitioning. With it, the main memory portion for user applications is initially a single contiguous block. When a new process is created, the exact amount of memory space is allocated to the process. As time goes on, there will appear many small holes in the main memory, which is referred to 6 as external fragmentation. Thus although much space is still available, it cannot be allocated to new processes. A method for overcoming external fragmentation is compaction. From time to time, the operating system moves the processes so that they occupy contiguous sections and all of the small holes are brought together to make a big block of space. The disadvantage of compaction is: The procedure is time-consuming and requires relocation capability. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 19

20 Address translation Figure shows the address translation procedure with dynamic partitioning, where the processor provides hardware support for address translation, protection, and relocation. The base register holds the entry point of the program, and may be added to a relative address to generate an absolute address. The bounds register indicates the ending location of the program, which is used to compare with each physical address generated. If the later is within bounds, then the execution may proceed; otherwise, an interrupt is generated, indicating illegal access to memory. The relocation can be easily supported with this mechanism with the new starting address and ending address assigned respectively to the base register and the bounds 7 register. Placement algorithm Different strategies may be taken as to how space is allocated to processes: First fit: Allocate the first hole that is big enough. Searching may start either at the beginning of the set of holes or where the previous first-fit search ended. Best fit: Allocate the smallest hole that is big enough. The entire list of holes must be searched unless it is sorted by size. This strategy produces the smallest leftover hole. Worst fit: Allocate the largest hole. In contrast, this strategy aims to produce the largest leftover hole, which may be big enough to hold another process. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 20

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22 Implementing Protection with Virtual Memory To enable the OS to implement protection in the VM system, the HW must: 1. Support at least two modes that indicate weather the running process is a user process (executive process) or an OS process (kernel/supervisor process). 2. provide a portion of the CPU state that a user process can read but not write (includes supervisor mode bit). 3. provide mechanism whereby the CPU can go from user mode to supervisor mode (accomplished by a system call exception) and vice versa (return from exception instruction). Only OS process can change page tables. Page tables are held in OS address space thereby preventing a user process from changing them. When processes want to share information in a limited way, the operating system must assist them. The write access bit (in both the TLB and the page table) can be used to restrict the sharing to just read sharing. Cache Misses A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 22

23 5.Discuss in detail about basic memory concepts(auc May 12) The maximum size of the memory in any computer is determined by the addressing scheme. Most modern computers are byte addressable. The Figure 4.1 shows the possible address assignments for a byte-addressable 32-bit computer The big-endian arrangement is used in the processor. The little-endian arrangement is used in Intel processors. Modern implementations of computer memory are rather complex and difficult to understand at the beginning. To simplify that we will see about traditional approaches and then proceed with latest approaches. 1. Data transfer between the memory an d the processor takes place through the use of two processor registers, usually called MAR (memory address register) and MDR (memory data register) 2. If MAR is k bits long and MDR is n bits long, then the memory unit may contain upto 2k addressable location. 3. During a memory cycle, n bits of data are transferred between the memory and the processor. 4. This transfer takes place over the processor bus, which has k address lines and n data lines. 5. The bus also includes the control lines Read/Write (R/W) and Memory Function completed (MFC) for coordinating data transfers. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 23

24 6. Other control lines are also added to indicate the number of bytes to be transferred. The connection between the processor and memory in shown schematically in Figure The Processor reads data from the memory by loading the address of the required memory location in to the MAR register and sets the R/W line to 1 8. The Memory responds by placing the data from the addressed location on to the data lines, and confirms this by asserting the MFC signal. 9. After receiving the MFC signal, the processor loads the data lines into the MDR register. 10. The processor writes data into a memory location by loading the address of the location into MAR and loading the data into MDR. A write operation sets the R/W line to If read or write operation involve consecutive address locations in the main memory, then a block transfer operation can be performed. Address space 16-bit : 216 = 64K mem. locations 32-bit : 232 = 4G mem. locations 40-bit : 240 = 1 T locations Terminology: Memory access time time between Read and MFC signals Memory cycle time min. time delay between initiation of two successive memory operations Internal Organization of memory chips Form of an array Word line & bit lines 16x8 organization : 16 words of 8 bits each A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 24

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26 DRAMS: Charge on a capacitor Needs Refreshing A single transistor dynamic memory cell A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 26

27 Synchronous DRAMs Synchronized with a clock signal The cell array is the same as in asynchronous DRAMs. The address and data connections are buffered by means of registers. The output of each sense amplifier is connected to a latch. A Read operation causes the contents of all cells in the selected row to be loaded into these latches. But, if only refreshing has to be done the contents of the latches are not changed. Data held in the latches that correspond to the selected column(s) are transferred into the data output register. SDRAMs have several different modes of operation, which can be selected by writing control information into a mode register. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 27

28 Latency and Bandwidth Transfers between the memory and the processor involve single words of data or small blocks. of words. Large blocks, constituting a page of data, are transferred between the memory and the disk. The speed and efficiency of these transfers have a large impact on the performance of a computer system. A good performance is indicated by two parameters latency and bandwidth. The memory latency is used to refer to the amount of time it takes to transfer a word of data to or from the memory. When transferring blocks of data, it is of interest to know much time is needed to transfer an entire block. Since blocks can be variable in size, it is useful to define performance in bits or bytes that can be transferred in one second. This measure is often referred to as the memory bandwidth. Double Data Rate SDRAM Since the SDRAM transfer data on both edges of the clock, their bandwidth is essentially doubled for long burst transfers. Such devices are known as double-data-rate SDRAMs (DDRSDRAMs) To make it possible to access the data at a high rate, the cell array is organized in two banks. Each bank can be accessed separately. Consecutive words of a given block are stored in different banks. Such interleaving of words allows simultaneous access to two words that are transferred on successive edges of the clock. Memory system considerations Cost Speed Power dissipation A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 28

29 Size of chip Memory controller Used Between processor and memory Refresh Overhead Memory hierarchy A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 29

30 Principle of locality: Temporal locality (locality in time): If an item is referenced, it will tend to be referenced again soon. Spatial locality (locality in space): If an item is referenced, items whose addresses are close by will tend to be referenced soon. Sequentiality (subset of spatial locality ). The principle of locality can be exploited implementing the memory of computer as a memory hierarchy, taking advantage of all types of memories. Method: The level closer to processor (the fastest) is a subset of any level. 6.Explain in detail about associative memory? Associative memory can also be called as Content addressable memory (CAM) CAM is accessed simultaneously and in parallel on the basis of data content rather than by specific address or location Associative memory is more expensive than a RAM because each cell must have storage capability as well as logic circuits Argument register holds an external argument for content matching Key register mask for choosing a particular field or key in the argument word Block digram of associative memory Single cell of associative memory A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 30

31 Associative mapped cache The first is the construction of a memory with storage cells that have the capability of performing simultaneously the functions of storage, nondestructive reading, and comparison. The second method of realizing an associative memory is the programmed organization (modeling) of the memory. It consists of the establishment of associative connections between the information contained in the memory by means of ordered arrangement of the information in the form of sequential chains or groups (lists) connected by linkage addresses whose codes are stored in the same memory cell. A. Joyce-AP/CSE-MAHALAKSHMI ENGINEERING COLLEGE Page 31