IDT71016S/NS. CMOS Static RAM 1 Meg (64K x 16-Bit)

Transcription

1 CMOS Static RAM 1 Meg (4K x 1-Bit) IDT711S/NS Features 4K x 1 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial and Industrial: //2 One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTLcompatible Low power coumption via chip deselect Upper and Lower Byte Enable Pi Commercial and industrial product available in 44-pin Plastic SOJ package and 44-pin TSOP package Description The IDT711 is a 147-bit high-speed Static RAM organized as 4K x 1. It is fabricated using IDT s high-perfomance high-reliability CMOS technology. This state-of-the-art technology combined with innovative circuit design techniques provides a cost-effective solution for high-speed memory needs. The IDT711 has an output enable pin which operates as fast as 7 with address access times as fast as. All bidirectional inputs and outputs of the IDT711 are TTL-compatible and operation is from a single V supply. Fully static asynchronous circuitry is used requiring no clocks or refresh for operation. The IDT711 is packaged in a JEDEC standard 44-pin Plastic SOJ and 44-pin TSOP Type II. Functional Block Diagram OE Output Enable A - A Address s Row / Column Decoders Chip Enable High Byte I/O I/O I/O Write Enable 4K x 1 Memory Array 1 See Amps and Write Drivers Low Byte I/O I/O 7 I/O BHE BLE Byte Enable s 321 drw 1 27 Integrated Device Technology Inc. 1 FEBRUARY 27 DSC-321/1

2 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Pin Configuratio Pin Descriptio A - A Address Inputs Input A A3 A2 A1 A I/O I/O 1 I/O 2 I/O 3 VCC VSS I/O 4 I/O I/O I/O 7 A A14 A13 A NC SO44-1 SO A A A7 OE BHE BLE I/O I/O 14 I/O 13 I/O VSS VCC I/O 11 I/O 1 I/O 9 I/O NC A A9 A1 A11 NC Chip Select Input Write Enable Input OE Output Enable Input BHE High Byte Enable Input BLE Low Byte Enable Input I/O - I/O Data Input/Output I/O VCC.V Power Pwr VSS Ground Gnd 321 tbl 1 SOJ/TSOP Top View 321 drw 2 Truth Table (1) OE BLE BHE I/O - I/O7 I/O - I/O Function H X X X X High-Z High-Z Deselected - Standby L L H L H High-Z Low Byte Read L L H H L High-Z High Byte Read L L H L L ` Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled NOTE: 1. H = VIH L = VIL X = Don't care. 321 tbl

3 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings (1) Symbol Rating Value Unit VTERM (2) Terminal Voltage with Respect to GND -. to +7. V TA Operating Temperature to +7 o C TBIAS TSTG Temperature Under Bias Storage Temperature - to + o C - to + o C PT Power Dissipation 1.2 W IOUT DC Output Current ma 321 tbl 3 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect reliability. 2. VTERM must not exceed VCC +.V. Recommended DC Operating Conditio NOTE: 1. VIL (min.) = 1.V for pulse width less than trc/2 once per cycle. DC Electrical Characteristics (VCC =.V ± 1% Commercial and Industrial Temperature Range) Recommended Operating Temperature and Supply Voltage Grade Temperature GND VCC Commercial C to +7 C V.V ± 1% Industrial 4 C to + C V.V ± 1% Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4... V GND Ground V VIH Input High Voltage 2.2 VDD +. V VIL Input Low Voltage -. (1). V 321 tbl Capacitance (TA = +2 C f = 1.MHz SOJ/TSOP Package) Symbol Parameter (1) Conditio Max. Unit CIN Input Capacitance VIN = 3dV pf CI/O I/O Capacitance VOUT = 3dV 7 pf NOTE: 321 tbl 1. This parameter is guaranteed by device characterization but not production tested. Symbol Parameter Test Conditio Min. Max. Unit 321 tbl 4 ILI Input Leakage Current VCC = Max. VIN = GND to VCC ILO Output Leakage Current VCC = Max. = VIH VOUT = GND to VCC µa µa VOL Output Low Voltage IOL = ma VCC = Min..4 V VOH Output High Voltage IOH = -4mA VCC = Min. 2.4 V DC Electrical Characteristics (1) (VCC =.V ± 1% VLC =.2V VHC = VCC.2V) 321 tbl 7 711S 711S 711S2 Symbol Parameter Com'l. Ind. Com'l. Ind. Com'l. Ind. Unit ICC ISB Dynamic Operating Current ma < VIL Outputs Open VCC = Max. f = fmax (2) Standby Power Supply Current (TTL Level) 4 4 ma > VIH Outputs Open VCC = Max. F = fmax (2) ISB1 Standby Power Supply Current (CMOS Level) > VHC Outputs Open VCC = Max. f = (2) VIN < VLC or VIN > VHC ma 1. All values are maximum guaranteed values. 2. fmax = 1/tRC (all address inputs are cycling at fmax); f = mea no address input lines are changing. 321 tbl.42 3

4 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges AC Test Conditio Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.V 1. 1.V 1.V See Figure 1 2 and tbl 9 AC Test Loads V V 4Ω 4Ω DATA OUT DATA OUT 3pF* 2Ω pf* 2Ω 321 drw drw 4 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz tolz tchz tohz tow and twhz) taa ta (Typical ) CAPACITANCE (pf) 321 drw Figure 3. Output Capacitive Derating.42 4

5 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VCC =.V ± 1% Commercial and Industrial Range) 711S 711S 711S2 Symbol Parameter Min. Max. Min. Max. Min. Max. Unit READ CYCLE trc Read Cycle Time 2 taa Address Access Time 2 ta Chip Select Access Time 2 tclz (1) Chip Select Low to Output in Low-Z 4 tchz (1) Chip Select High to Output in High-Z toe Output Enable Low to Output Valid 7 1 tolz (1) Output Enable Low to Output in Low-Z tohz (1) Output Enable High to Output in High-Z toh Output Hold from Address Change 4 4 tbe Byte Enable Low to Output Valid 7 1 tblz (1) Byte Enable Low to Output in Low-Z tbhz (1) Byte Enable High to Output in High-Z WRITE CYCLE twc Write Cycle Time 2 taw Address Valid to End of Write 9 1 tcw Chip Select Low to End of Write 9 1 tbw Byte Enable Low to End of Write 9 1 tas Address Set-up Time twr Address Hold from End of Write twp Write Pulse Width 9 1 tdw Data Valid to End of Write 7 1 tdh Data Hold Time tow (1) Write Enable High to Output in Low-Z twhz (1) Write Enable Low to Output in High-Z NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization but is not production tested. 321 tbl 1 Timing Waveform of Read Cycle No. 1 trc toh taa toh PREVIOUS VALID 1. is HIGH for Read Cycle. 2. Device is continuously selected is LOW. 3. OE BHE and BLE are LOW. VALID 321 drw.42

6 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2 (1) trc taa toh OE toe tolz tohz (2) ta tclz tchz BHE BLE (2) tbe tblz tbhz DATA OUT VALID 1. is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of BHE or BLE traition LOW; otherwise taa is the limiting parameter. 3. Traition is measured ±2mV from steady state. 321 drw 7 Timing Waveform of Write Cycle No. 1 ( Controlled Timing) (4) twc taw (2) tcw tbw () tchz BHE BLE twp twr () tbhz tas PREVIOUS DATA VALID () twhz tdw () tow tdh DATA VALID DATAIN DATAIN VALID 321 drw 1. A write occurs during the overlap of a LOW LOW BHE or BLE and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle this requirement does not apply and the minimum write pulse is as short as the specified twp. 3. During this period I/O pi are in the output state and input signals must not be applied. 4. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition the outputs remain in a high-impedance state.. Traition is measured ±2mV from steady state..42

7 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 ( Controlled Timing) (14) twc taw BHE BLE tas (2) tcw twp tbw twr DATAIN tdw DATAIN VALID tdh 321 drw 9 Timing Waveform of Write Cycle No. 3 (BHE BLE Controlled Timing) (14) twc taw BHE BLE tas (2) tcw tbw twp twr tdw tdh DATAIN DATAIN VALID 321 drw 1 1. A write occurs during the overlap of a LOW LOW BHE or BLE and a LOW. 2. OE is continuously HIGH. If during a controlled write cycle OE is LOW twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle this requirement does not apply and the minimum write pulse is as short as the specified twp. 3. During this period I/O pi are in the output state and input signals must not be applied. 4. If the LOW or BHE and BLE LOW traition occurs simultaneously with or after the LOW traition the outputs remain in a high-impedance state.. Traition is measured ±2mV from steady state..42 7

8 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 711 N S XX XXX X X Device Type Power Speed Package Process/ Temperature Range Blank I G Y PH Commercial ( C to +7 C) Industrial (-4 C to + C) Restricted hazardous substance device. 4-mil SOJ (SO44-1) 4-mil TSOP Type II (SO44-2) 2 Speed in nanoseconds Blank N First generation or current die step Current generation die step (Optional) 321 drw 11.42

9 IDT711 CMOS Static RAM 1 Meg (4K x 1-bit) Commercial and Industrial Temperature Ranges Datasheet Document History 7/3/99 Updated to new format //99 Pg. 3 Expressed commercial and industrial ranges on DC Electrical table Removed Icc ISB and ISB1 values for S industrial speed Pg. Expressed commercial and industrial ranges on AC Electrical table Changed footnote #2 to commercial temperature only Pg. Revised footnotes on Write Cycle No. 1 diagram Pg. 7 Pg. Revised footnotes on Write Cycle No. 2 and No. 3 diagrams Removed SCD 272 footnote Added commercial only for speed /13/99 Pg. 9 Added Datasheet Document History 9/3/99 Pg. 3 Added industrial temperature speed grade offering /9/ Not recommended for new desig 2/1/1 Removed "Not recommended for new desig" 1/3/4 Pg. Added "Restricted hazardous substance device" to order information. 1/3/ Pg. 3 Updated Capacitance table to include TSOP. 2/13/7 Pg. Added N generation die step to data sheet ordering information. CORPORATE HEADQUARTERS for SALES: for Tech Support: 24 Silver Creek Valley Road or ipchelp@idt.com San Jose CA fax: The IDT logo is a registered trademark of Integrated Device Technology Inc..42 9