Digital Fundamentals. Integrated Circuit Technologies

Transcription

1 Digital Fundamentals Integrated Circuit Technologies 1

2 Objectives Determine the noise margin of a device from data sheet parameters Calculate the power dissipation of a device Explain how propagation delay affects the frequency of operation or speed of a circuit Interpret the speed-power product as a measure of performance Use data sheets to obtain information about a specific device Explain what the fan-out of a gate means Describe how basic TTL and CMOS gates operate at the component level Recognize the difference between TTL totem-pole outputs and TTL open-collector outputs and understand the limitations and uses of each Connect circuits in a wired-and configuration Describe the operation of tristate circuits Properly terminate unused gate inputs Compare the performance of TTL and CMOS families Handle CMOS devices without risk of damage due to electrostatic discharge State the advantages of ECL Describe PMOS and NMOS circuits Describe an E 2 CMOS cell 2

3 Basic Operational Characteristics and Parameters for Integrated Circuit Technologies DC Supply Voltage CMOS Logic Levels TTL Logic Levels Noise Immunity Noise Margin Power Dissipation Propagation Delay Speed-Power Product Loading and Fan-Out CMOS Loading 3

4 Figure Example of V CC and ground connection and distribution in an IC package. Other pin connections are omitted for simplicity. 4

5 Figure Input and output logic levels for CMOS. 5

6 Figure Input and output logic levels for TTL. 6

7 Figure Illustration of the effects of input noise on gate operation. 7

8 Figure Illustration of noise margins. Values are for 5 V CMOS, but the principle applies to any logic family. 8

9 Figure Currents from the dc supply. 9

10 Figure Power-versus-frequency curves for TTL and CMOS. 10

11 Figure A basic illustration of propagation delay. 11

12 Figure Propagation delay times. 12

13 Figure Loading a gate output with gate inputs. 13

14 Figure Capacitive loading of a CMOS gate. 14

15 Figure Basic illustration of current sourcing and current sinking in logic gates. 15

16 Figure HIGH-state TTL loading. 16

17 Figure LOW-state TTL loading. 17

18 CMOS Circuits MOSFET CMOS Inverter CMOS NAND Gate CMOS NOR Open Drain Gates Tristate CMOS Gates 18

19 Figure Basic symbols and switching action of MOSFETs. 19

20 Figure Simplified MOSFET symbol. 20

21 Figure A CMOS inverter circuit. 21

22 Figure Operation of a CMOS inverter. 22

23 Figure A CMOS NAND gate circuit. 23

24 Figure A CMOS NOR gate circuit. 24

25 Figure Open-drain CMOS gates. 25

26 Figure The three states of a tristate circuit. 26

27 Figure A tristate CMOS inverter. 27

28 Figure Handling unused CMOS inputs. 28

29 TTL circuits Bipolar Junction Transistors TTL Inverter TTL NAND Gate Open-Collector Gate Tristate TTL Gate Schottky TTL 29

30 Figure a BJT. The symbol for 30

31 Figure The ideal switching action of the BJT. 31

32 Figure A standard TTL inverter circuit. 32

33 Figure Operation of a TTL inverter. 33

34 Figure A TTL NAND gate circuit. 34

35 Figure Diode equivalent of a TTL multiple-emitter transistor. 35

36 Figure TTL inverter with open-collector output. 36

37 Figure Open-collector symbol in an inverter. 37

38 Figure Basic tristate inverter circuit. 38

39 Figure An equivalent circuit for the tristate output in the high-z state. 39

40 Figure Schottky TTL NAND gate. 40

41 Practical Considerations in the use of TTL Current Sinking and Current Sourcing Using Open-Collector Gates for Wired- AND operation Connection of Totem-pole Outputs Open-Collectors Buffer/Drivers Unused TTL Inputs 41

42 Figure Current sinking and sourcing action in TTL. 42

43 Figure A wired-and configuration of four inverters. 43

44 Figure Open-collector wired negative-and operation with inverters. 44

45 Figure Example 15-5: Write the output expression for the wired-and configuration of open-collector AND gates (see below) X = ABCDEFGH 45

46 Figure Example 15-6: a) write the logic expression for X, b) Determine the min value of R p if I OL(max) for each gate is 30 ma and V OL(max) is 0.4V X=ABCDEF I R P = 23.6mA R p = 195Ω 46

47 Figure Totem-pole outputs wired together. Such a connection may cause excessive current through Q 1 of device A and Q 2 of device B and should never be used. 47

48 Figure Some applications of open-collector drivers. 48

49 Figure Example 15-7: Determine the value of the limiting resistor, RL; LED current is 20mA, 1.5V drop in the LED, 0.1V LOW-state output of the gate VR L = 3.4V R L = 170Ω 49

50 Figure Comparison of an open TTL input and a HIGH-level input. 50

51 Figure Methods for handling unused TTL inputs. 51

52 Comparison of CMOS and TTL Performance 52

53 Figure An ECL OR/NOR gate circuit. 53

54 Comparison of ECL with TTL and CMOS 54

55 PMOS, NMOS, and E 2 CMOS PMOS - one of the first high density MOS technologies NMOS circuits were developed as processing technology improved E 2 MOS combined the CMOS and NMOS technologies, this is used in the GALs of chapter 7 and 11 55

56 Figure Basic PMOS gate. 56

57 Figure Two NMOS gates. 57

58 Figure An E 2 CMOS cell. 58

59 SUMMARY 59