Philip Andrew Simpson. FPGA Design. Best Practices for Team-based Reuse. Second Edition

Transcription

1 FPGA Design

2

3 Philip Andrew Simpson FPGA Design Best Practices for Team-based Reuse Second Edition

4 Philip Andrew Simpson San Jose, CA, USA ISBN DOI / ISBN (ebook) Library of Congress Control Number: Springer Cham Heidelberg New York Dordrecht London Springer International Publishing Switzerland 2010, 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer International Publishing AG Switzerland is part of Springer Science+Business Media (

5 Contents 1 Introduction Project Management The Role of Project Management Project Management Phases Estimating a Project Duration Schedule Design Specification Design Specification: Communication Is Key to Success High Level Functional Specification Functional Design Specification System Modeling Definition of System Modeling What is SystemC? Classes of SystemC Models Untimed (UT) Loosely-Timed (LT) Approximately Timed (AT) Cycle Accurate Software Development Using Virtual Targets SystemC Basics SC_Module Ports Process SC_CTOR SC_METHOD SystemC Tesbenches Resource Scoping Introduction Engineering Resources v

6 vi Contents 5.3 Third Party IP Device Selection Silicon Specialty Features Density Speed Requirements Pin-Out Power Availability of IP Availability of Silicon Summary Design Environment Introduction Scripting Environment Make Files Tcl Scripts Automation Easier Project Maintenance and Documentation Interaction with Version Control Software Use of a Problem Tracking System A Regression Test System When to Upgrade the Versions of the FPGA Design Tools Common Tools in the FPGA Design Environment High-Level Synthesis Load Sharing Software Board Design Challenges That FPGAs Create for Board Design Engineering Roles and Responsibilities FPGA Engineers PCB Design Engineer Signal Integrity Engineer Power and Thermal Considerations Filtering Power Supply Noise Power Distribution Signal Integrity Types of Signal Integrity Problems Electromagnetic Interference (EMI) Design Flows for Creating the FPGA Pinout User Flow 1: FPGA Designer Driven User Flow How Do FPGA and Board Engineers Communicate Pin Changes? Board Design Check List for a Successful FPGA Pin-out... 64

7 Contents vii 8 Power and Thermal Analysis Introduction Power Basics Static Power Dynamic Power I/O Power Inrush Current Configuration Power Key Factors in Accurate Power Estimation Accurate Power Models of the FPGA Circuitry Accurate Toggle Rate Data on Each Signal Accurate Operating Conditions Resource Utilization Power Estimation Early in the Design Cycle (Power Supply Planning) Simulation Based Power Estimation (Design Power Verification) Partial Simulations Best Practices for Power Estimation Team Based Design Flow Introduction Recommended Team Based Design Flow Overview Design Set-up Creation of Top-Level Project Partitioning of the Design Timing Budgets Physical Partitioning/Floorplan Design Place and Route Design Create Project for Partitions/Other Team Members Team Member Development Flow Team Leader Design Integration Working with Version Control Software Team Based Design Checklist RTL Design Introduction Common Terms and Terminology Recommendations for Engineers with an ASIC Design Background Recommended FPGA Design Guidelines Synchronous vs. Asynchronous Global Signals Dedicated Hardware Blocks Managing Metastability... 98

8 viii Contents 10.5 Writing Effective HDL What s the Best Language Documented Code Recommended Signal Naming Convention Hierarchy and Design Partitioning Design Reuse Techniques for Reducing Design Cycle Time Design for Debug RTL Coding Styles for Synthesis General Verilog Guidelines General VHDL Guidelines RTL Coding for Performance RTL Coding for Area Synthesis Tool Settings Inference of RAM Inference of ROMs Inference of DSP Blocks Inference of Registers Avoiding Latches Analyzing the RTL Design Synthesis Reports Messages Block Diagram View Recommended Best Practices for RTL Design IP and Design Reuse Introduction The Need for IP Reuse Benefits of IP Reuse Challenges in Developing a Design Reuse Methodology Make Versus Buy Architecting Reusable IP Specification Implementation Methods Use of Standard Interfaces Packaging of IP Documentation User Interface Compatibility with System Integration Tools Constraint Files IP Integration File Formats IP Security IP Reuse Checklist

9 Contents ix 12 Embedded Design Definition of an Embedded Design Advantages That FPGA Devices Provide for Embedded Design Challenges in a FPGA Based Embedded Design Embedded Hardware Design Endianness Busses Bus Arbitration Schemes Hardware Verification Using Simulation Hardware to Software Interface Definition of Register Address Map Software Interface Use of the Register Address Map Summary Embedded SW Design Firmware Development Application Software Development Use of Operating Systems SW Tools Use of FPGA System Integration Tools for Embedded Design Functional Verification Introduction Challenges of Functional Verification Glossary of Verification Concepts RTL Versus Gate Level Simulation Verification Methodology Attack Complexity Functional Coverage Directed Testing Random Dynamic Simulation Constrained Random Tests Use of SystemVerilog for Design and Verification General Testbench Methods Self Verifying Testbenches Formal Equivalency Checking Code Coverage QA Testing Functional Regression Testing GUI Testing for Reusable IP

10 x Contents Hardware Interoperability Tests Hardware/Software Co-verification Getting to Silicon Fast Functional Verification Checklist Timing Closure Timing Closure Challenges The Importance of Timing Assignments and Timing Analysis Background Basics of Timing Analysis A Methodology for Successful Timing Closure Family and Device Assignments Design Planning Early Timing Estimation CAD Tool Settings Compilation Reports and Analysis Tools Floorplanning Tools Miscellaneous Techniques Analysis of Common Timing Closure Failures Missing Timing by a Small Margin Review of Compilation Results and Messages Synthesis and Physical Synthesis Global Signals High Fan-out Registers Routing Congestion Clustering Assignments Missing Timing Constraints Conflicting Timing Constraints Long Compile Times Design Planning, Implementation, Optimization and Timing Closure Checklist High Level Design High Level Design Algorithmic Synthesis C to Gates SystemC to Gates OpenCL Summary In-System Debug In-System Debug Challenges Plan for Debug

11 Contents xi 16.3 Techniques Use of Pins for Debug External Logic Analyzer Internal Logic Analyzer Use of Debug Logic Editing Memory Contents Use of a Soft Processor for Debug Power-Up Debug Debug of Transceiver Interfaces Reporting of System Performance Debug of Soft Processors Device Programming Issues Hardware/Software Debug In-System Debug Checklist Design Sign-off Sign-off Process After Sign-off Bibliography