4 Multiplexer. Y Fig Keyboard Scan Matrix

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1 - 4 Multiplexer Microcontroller 3 Decoder X Y Fig. - Keyboard Scan Matrix 2 Prentice Hall, Inc.

2 -2 Track Sector Head positioning Fig. -2 Hard Disk Format 2 Prentice Hall, Inc.

3 -3 RGB electron guns R G B Pixel Scan line Fig. -3 CRT Display 2 Prentice Hall, Inc.

4 -4 Central processing unit (CPU) Address bus Control Interface Interface Interface Interface Keyboard CRT display Printer Magnetic disk Input device Output device Output device Fig. -4 Connection of I/O Devices to CPU Input and output device 2 Prentice Hall, Inc.

5 -5 Bidirectional data bus Bus buffers Port A register I/O data Chip select Register select I/O read CS RS RS RD Timing and control Internal bus Port B register Control register I/O data Control lines I/O write WR Status register Status lines To CPU To I/O device CS RS RS Register selected x x None: data bus in high-impedance state Port A register Port B register Control register Status register 2 Prentice Hall, Inc. Fig. -5 Example of I/O Interface Unit

6 -6 Destination unit Strobe Source unit Strobe (a) Destination-initiated transfer Source unit Strobe Destination unit Strobe (b) Source-initiated transfer Fig. -6 Asynchronous Transfer Using Strobing 2 Prentice Hall, Inc.

7 -7 Destination unit Request Reply Source unit Request Reply (a) Destination-initiated transfer Source unit Request Reply Destination unit Request Reply (b) Source-initiated transfer Fig. -7 Asynchronous Transfer Using Handshaking 2 Prentice Hall, Inc.

8 -8 Start bit Character bits Fig. -8 Format of Asynchronous Serial Transfer of Data Stop bits 2 Prentice Hall, Inc.

9 -9 I/O write Keyboard controller and interface Keyboard CPU I/O read Address bus Interrupt request Input register Output register Control register Microcontroller Power Keyboard clock Keyboard serial data Ground Microcontroller Status register Fig. -9 Keyboard Controller and Interface 2 Prentice Hall, Inc.

10 - Computer Root Hub Monitor Printer Hub Hub Keyboard Hub Hub Scanner Mouse Joystick Microphone Speaker Speaker Fig. - I/O Device Connection Using the Universal Serial Bus (USB) 2 Prentice Hall, Inc.

11 - Data NRZI Fig. - Non-Return to Zero Inverted Data Representation 2 Prentice Hall, Inc.

12 -2 SYNC PID Packet Specific Data CRC EOP (a) General packet format SYNC 8 bits Type 4 bits Check 4 bits Device Address 7 bits Endpoint Address 4 bits CRC EOP (b) Output packet SYNC 8 bits Type 4 bits Check 4 bits Data (Up to 24 bytes) CRC EOP (c) Data packet (Data type) SYNC 8 bits Type 4 bits Check 4 bits EOP (d) Handshake packet (Acknowledge type) Fig.-2 USB Packet Formats 2 Prentice Hall, Inc.

13 -3 CPU Address bus I/O read Interface Data register I/O bus Ready I/O device I/O write Status register Acknowledge Flag Fig. -3 Data Transfer from I/O Device to CPU 2 Prentice Hall, Inc.

14 -4 Read status register Check flag bit Flag Read data register Transfer data to memory Operation complete? No Yes Continue program Fig. -4 Flowchart for CPU Program to Input Data 2 Prentice Hall, Inc.

15 -5 CPU data bus VAD VAD VAD 2 Device PI PO Device PI PO Device 2 PI PO To next device Interrupt request CPU Interrupt acknowledge Fig. -5 Daisy Chain Priority Interrupt 2 Prentice Hall, Inc.

16 -6 PI Priority in Enable VAD Vector address Interrupt request from device S R RF Priority out PO Delay Interrupt request to CPU PI RF PO Fig. -6 One Stage of the Daisy Chain Priority Arrangement Enable 2 Prentice Hall, Inc.

17 -7 Highest priority Interrupt register 3 D 3 Interrupt acknowledge from CPU Lowest priority 2 D 2 D Priority encoder Figure 3-7 A A 3 D 2 V Mask register VAD Interrupt to CPU Fig. -7 Parallel Priority Interrupt Hardware 2 Prentice Hall, Inc.

18 -8 Bus request Bus granted BR BG CPU AB DB RD Address bus Read High impedance (disabled) if BG = WR Write Fig. -8 CPU Bus Control Signals 2 Prentice Hall, Inc.

19 -9 Address bus buffers Address bus buffers DMA select Register select Read DS RS RD Internal bus Address register Word-count register Write Bus request WR BR Control logic Control register Bus granted Interrupt BG DMA request DMA acknowledge to I/O device Fig. -9 Block Diagram of a DMA Controller 2 Prentice Hall, Inc.

20 -2 Interrupt BG BR CPU Memory RD WR Address Data RD WR Address Data Read control Write control Address bus Address decoder RD WR Address Data DS RS BR BG Interrupt DMA controller DMA request DMA acknowledge I/O peripheral device Fig. -2 DMA Transfer in a Computer System 2 Prentice Hall, Inc.

21 -2 Memory unit Memory bus Peripheral devices PD PD PD PD Central processing unit (CPU) Input-output processor (IOP) I/O bus Fig. -2 Block Diagram of a Computer with I/O Processor 2 Prentice Hall, Inc.

22 -22 CPU operations IOP operations Send instruction to test IOP path Transfer status word to memory location If status O.K., send start I/O instruction to IOP Access memory for IOP program CPU continues with another program Conduct I/O transfers using DMA: prepare status report I/O transfer completed; interrupt CPU Request IOP status Transfer status word to memory location Check status word for correct transfer Continue 2 Prentice Hall, Inc. Fig. -22 CPU-IOP Communication

INPUT-OUTPUT ORGANIZATION

1 INPUT-OUTPUT ORGANIZATION Peripheral Devices Input-Output Interface Asynchronous Data Transfer Modes of Transfer Priority Interrupt Direct Memory Access Input-Output Processor Serial Communication 2