Migration Guide: Numonyx Synchronous StrataFlash Memory (K3) to Numonyx StrataFlash Wireless (L18/L30) Memory

Transcription

1 Migration Guide: Numonyx Synchronous StrataFlash Memory (K3) to Numonyx StrataFlash Wireless (L18/L30) Memory Application Note November

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright 2007, Numonyx B.V., All Rights Reserved. Application Note November

3 Contents 1.0 Introduction Features Comparison Package and Ballouts Design Considerations Hardware Design Considerations Software Design Considerations Program/Erase Operations Write State Machine Program and Erase Characteristics Design Tools Numonyx Flash Software A Additional Information November 2007 Application Note

4 Revision History Date of Revision Revision Description 03/8/ Original version 9/27/ Customer release 02/13/ Revised L18/L30 256Mb partition size Revised Top and Bottom Memory Maps Added L18/L30 WAIT signal function Added WAIT Designs Considerations November Applied Numonyx branding. Application Note November

5 1.0 Introduction This application note describes the process for migrating from the Numonyx Synchronous StrataFlash memory device (K3/K18) to the Numonyx StrataFlash wireless memory device (L18/L30). Considerations for implementing new features of the L18/L30 device into an existing K3/K18 design are discussed. The L18/L30 device combines reliable and proven two-bit-per-cell technology with multi-partition read-while-write (RWW)/ read-while-erase (RWE) dual operation. It provides high-performance asynchronous page and synchronous burst read modes using 1.8 volt low-voltage, multi-level cell (MLC) technology. It is a 1.8 volt device (V CC ), but has two I/O voltage versions: 1.8 volt V CCQ (L18) and 3 volt V CCQ (L30). Available densities range from 64Mbit to 256Mbit, providing high value with low-power performance. This document was written based on advance device information available at the time. Any changes in specifications to either device may not be reflected in this document. Refer to the appropriate documents or sales personnel for the most current product information before finalizing any design. 2.0 Features Comparison The L18/L30 device has several features not available on K3/K18. This includes multipartitioning for hardware RWW/RWE, smaller blocks for code applications, wider operating voltage ranges, lower core voltage, and improved AC/DC specifications. Table 1 compares the various features and specifications of each device. Table 1: Device Comparison (Sheet 1 of 2) Specification Feature Numonyx Synchronous StrataFlash Memory (K3/K18) Numonyx StrataFlash Wireless Memory 64Mbit Device Density Partition Architecture Operating Voltage Range 128Mbit 256Mbit Partitioning Single Partition Multiple Parameter Blocks None Four 16KWord Main Blocks 64KWord 64KWord Top or Bottom Parameter Partition V CC 2.7 V to 3.6 V 1.7 V to 2.0 V V CCQ V PP 1.65 V to 1.95 V V to 3.6 V 1.35 V to 2.0 V 1.70 V to 2.0 V 2.20 V to 3.3 V 8.5 V to 9.5 V November 2007 Application Note Order Number:

6 Table 1: Device Comparison (Sheet 2 of 2) Specification Feature Numonyx Synchronous StrataFlash Memory (K3/K18) Numonyx StrataFlash Wireless Memory Performance Security Commands Program Erase Asynchronous Initial Access (t AVQV ) Bin 1/ Bin ns (64Mb) 115 ns (128Mb) 120 ns (256Mb) 85 ns/ 95 ns Synchronous Burst Access (t CHQV ) 13 ns/ 16 ns 14 ns Asynchronous Page Access (t APA ) 25 ns (8-word page) 25 ns (4-word page) 4-Word Burst 8-Word Bust 16-Word burst Cont. Word Burst Burst Suspend Mode No Program Suspend (typ/ max) 20 µs/ 25 µs 20 µs/ 25 µs Erase Suspend (typ/ max) 20 µs/ 25 µs 20 µs/ 25 µs OTP Space 128 bits + 2K bits 128 bits + 2K bits Flexible Block Locking No No Basic Command Set (BCS) Common Flash Interface (CFI) Word Program Buffered Program (64 Byte) Buffered Enhanced Factory Program V PP Write Protect V PEN Cycles 100, ,000 Block Erase Command Temperature Operating Temperature 40 C to +85 C 25 C to +85 C 16-bit data bus I/O Bus Package Process WAIT Output Active WAIT Asserted in Asynchronous and Synchronous Non-Array Read, Write WAIT Active in Synchronous Array Read OE#-high has no effect on WAIT) Active WAIT De-asserted in Asynchronous Reads, and all Writes WAIT Active in Synchronous Array and Non-Array Read OE#-High: WAIT High-Z OE#-Low: WAIT Active (See Note) 64Mbit: VFBGA (7x8) 7.7 mm x 9.0 mm 7.7 mm x 9.0 mm 128Mbit: VFBGA (7x8) 11.0 mm x 9.0 mm 7.7 mm x 9.0 mm 256Mbit: VFBGA (7x9) 14.5 mm x 9.0 mm 11.0 mm x 9.0 mm 0.18 µm No 0.13 µm No Note: See WAIT Section , Read Cycles - K3/K18 on page 9 for more details. Application Note November Order Number:

7 3.0 Package and Ballouts The L18/L30 device is available in the VF BGA package for the 64-Mbit, 128-Mbit, and 256-Mbit densities, providing socket compatibility with K3/K18 flash memory. Figure 1 shows the device ballout for the 64- and 128-Mbit devices, and Figure 2 shows the 256-Mbit device. Figure 1: 7 x 8 Ball Matrix for 64- and 128-Mb Densities A A A 11 A 8 v SS v CC v PP A 18 A 6 A 4 A 4 A 6 A 18 v PP v CC V SS A 8 A 11 B B A 12 A 9 A 20 CLK RST# A 17 A 5 A 3 A 3 A 5 A 17 RST# CLK A 20 A 9 A 12 C C A 13 A 10 A 21 ADV# WE# A 19 A 7 A 2 A 2 A 7 A 19 WE# ADV# A 21 A 10 A 13 D D A 15 A 14 WAIT A 16 DQ 12 WP# A 22 A 1 A 1 A 22 WP# DQ 12 A 16 WAIT A 14 A 15 E E V CCQ DQ 15 DQ 6 DQ 4 DQ 2 DQ 1 CE# A 0 A 0 CE# DQ 1 DQ 2 DQ 4 DQ 6 DQ 15 V CCQ F F V SS DQ 14 DQ 13 DQ 11 DQ 10 DQ 9 DQ 0 OE# OE# DQ 0 DQ 9 DQ 10 DQ 11 DQ 13 DQ 14 V SS G G DQ 7 V SSQ DQ 5 v CC DQ 3 V CCQ DQ 8 V SSQ V SSQ DQ 8 V CCQ DQ 3 V CC DQ 5 V SSQ DQ 7 Top View - Ball Side Down Complete Ink Mark Not Shown Bottom View - Ball Side Up November 2007 Application Note Order Number:

8 Figure 2: 7 x 9 Ball Matrix for 256Mb Density A A11 A8 VSS VCC VPP A18 A6 A4 RFU RFU VCC A4 A6 A18 VPP VSS A8 A11 A B A12 A9 A20 CLK RST# A17 A5 A3 RFU RFU CLK A3 A5 A17 RST# A20 A9 A12 B C C A13 A10 A21 ADV# WE# A19 A7 A2 A25 A25 A2 A7 A19 WE# ADV# A21 A10 A13 D A15 A14 WAIT A16 D12 WP# A22 A1 A24 A24 A1 A22 WP# D12 A16 WAIT A14 A15 D E E VCCQ D15 D6 D4 D2 D1 CE# A0 A23 A23 A0 CE# D1 D2 D4 D6 D15 VCCQ F VSS D14 D13 D11 D10 D9 D0 OE# RFU RFU D11 OE# D0 D9 D10 D13 D14 VSS F G D7 VSSQ D5 VCC D3 VCCQ D8 VSSQ RFU RFU VSSQ D8 VCCQ D3 VCC D5 VSSQ D7 G Top View - Ball Side Down Complete Ink Mark Not Shown Bottom View - Ball Side Up Note: On lower density devices upper address balls can be treated as RFU's. (A24 is for 512Mb and A25 is for 1Gb densities). All ball locations are populated. 4.0 Design Considerations Today's high performance, low voltage burst CPU's and ASIC's designed for wireless applications place demands on the system s memory for increased data transfer speeds, while reducing the overall system power consumption and costs. The L18/L30 device satisfies these requirements with its multi-partition architecture, hardware readwhile-write, and 1.8 volt operation. In some cases, only minor hardware and/or software changes are needed to accommodate blocking and partitioning differences. For detailed hardware and software device information and specifications refer to the respective devices datasheet. 4.1 Hardware Design Considerations This section describes hardware design considerations when migrating from the K3/K18 device to the L18/L30 device AC Read Specifications Refer to the latest K3/K18 flash memory datasheet and the L18/L30 device datasheet when comparing read-timing specifications AC Write Specifications Refer to the latest K3/K18 flash memory datasheet and the L18/L30 device datasheet when comparing write-timing specifications. Application Note November Order Number:

9 4.1.3 I/O Signals All control and I/O signals of the L18/L30 device function identically to those of the K3/ K18 flash memory device except for WAIT VPEN, and VPP. Table 2compares the WAIT behavior of each device. Also, Section 4.1.4, WAIT Signal Function on page 9 describes how WAIT operates on L18/L30 as compared to K3/K18 devices. Table 3 summarizes VPEN and VPP operations. For density upgrades with L18/L30, the additional upper address signals must be connected as necessary to the system s upper address lines WAIT Signal Function During synchronous array reads and synchronous non-array reads, the WAIT signal functions differently on L18/L30 as compared to W18/W30. Table 2 summarizes these WAIT signal differences between W18/W30 and L18/L30. Table 2: WAIT Behavior Comparison Condition Numonyx Synchronous StrataFlash Memory (K3/K18) L18/L30 CE# = V IH High-Z High Z CE# = V IL Driven 1 Driven 1 OE# = V IH No Effect High Z OE# = V IL No Effect Driven 1 Synchronous Array Reads Active 2 Active 2 Synchronous Non-array Reads Asserted Active 2 All Asynchronous Reads and All Writes Asserted De-asserted Notes: 1. WAIT output driver is turned on, however the logic level of WAIT depends on the operational mode (e.g., sync/async read, write) of the device. WAIT is active when both CE# and OE# are asserted. 2. Active: WAIT is asserted until data becomes valid, then de-asserted Read Cycles - K3/K18 WAIT is active (Low-Z) whenever CE# is V IL, and floated (High-Z) when the device is not selected (CE# = V IH ). This enables other system components WAIT outputs to be connected with WAIT in order to drive the processor s data ready input. WAIT will always transition between High-Z and Low-Z asynchronously with respect to CE#. WAIT is asserted during asynchronous and synchronous non-array reads (RCR[15] = 1). During synchronous array reads (RCR[7] = 0), WAIT is asserted during the initial access latency period. WAIT deasserts when valid array data is output on AD[15:0] Read Cycles - L18/L30 WAIT behaves differently on L18/L30 compared to W18/W30 during synchronous nonarray reads (i.e. Read Status Register, Read Device ID, CFI Query). On L18/L30, WAIT is high-z when OE# = V IH, and active when OE# = V IL. WAIT behaves the same for synchronous non-array reads and synchronous array reads. During synchronous non-array reads, the same data word is output on successive clock edges until the burst length requirement is satisfied. November 2007 Application Note Order Number:

10 Hardware and software modifications for the system design are required in order to properly handle WAIT behavior differences during synchronous array and non-array operations when migrating to L18/L30 from W18/W Write Cycles - K3/K18 When operating in asynchronous mode, the WAIT signal will always be asserted during write cycles when the device is selected by a CE# assertion (CE# low) Write Cycles - L18/L30 When operating in asynchronous mode, the WAIT signal will always be deasserted during write cycles when the device is selected by a CE# assertion (CE# low). When operating in synchronous mode, the WAIT signal state will be deasserted when writing to a partition that is not in the Read-array mode, although the signal will only deassert after a valid clock edge during that cycle (prior to a valid clock edge at the beginning of the cycle, the WAIT signal will be asserted). When operating in synchronous mode and writing to a partition that is in Read-array mode, the WAIT signal will be asserted until the partition leaves the Read-array mode. For an example of WAIT during write cycles in synchronous mode, consider a program operation to a partition that is in the Read-array mode. When CE# is asserted to start the write cycle, the WAIT signal will also be asserted. If there is no clock toggling, the WAIT signal state will remain asserted. When the write cycle completes, the partition will change to Status mode, which will cause the WAIT signal to change to a deasserted state during the next cycle with respect to a valid clock edge WAIT Designs Considerations Synchronous flash memory devices drive WAIT whenever CE# and OE# are asserted. A totem pole output-driver design is used for the WAIT output signal to achieve fast high/low switching times of less than one clock period during synchronous read operations. Figure 3 shows a representative WAIT output driver arrangement. Application Note November Order Number:

11 Figure 3: WAIT Output Driver V CCQ (High) Q1 WAIT (Low) Q2 In order to achieve higher flash densities, systems use multiple flash devices or devices that feature silicon stacking technology. Silicon stacking is not only a popular way of doubling the density of flash devices, but it also conserves valuable PCB area in spaceconstrained designs. Multiple flash devices and silicon stacking can create situations where multiple WAIT signals are tied together in order to drive a processor s single DATA READY input. Signal contention can occur when more than one device is enabled simultaneously. There are several recommended options to alleviate this WAIT-signal contention when using multiple synchronous flash devices. Figure 4: In systems designed with multiple WAITs tied together and connected to a single DATA READY input, care must be taken to ensure only one flash device is enabled at any given time. Figure 4 shows the timing sequence when disabling a device (Flash A) prior to enabling another device (Flash B). System designers should consider t EHTZ when determining the device-to-device CE#-timing interval. Chip Select Timing Interval Flash A: CE# t EHTZ Flash B: CE# November 2007 Application Note Order Number:

12 Figure 5: Multiple WAIT outputs can be tied together through the use of external logic. This approach ensures logic isolation between WAIT outputs with no signal contention. Figure 5 illustrates an example of external logic using light pull-up resistors (>100K) to ensure the output of the AND gate is high when both Flash A and Flash B are deselected, causing their WAIT outputs to be High-Z simultaneously. WAIT Output Isolation Flash A System Processor +V WAIT A DATA READY Flash B +V WAIT B Table 3: Signal VPEN VPP VPEN/ VPP Operation Summary Numonyx Synchronous StrataFlash Memory (K3/K18) PROGRAM/ ERASE/ BLOCK LOCK ENABLE: A logic-level input, VPEN controls device protection. VPEN must be driven- do not float. When V PEN VPENLK (Lockout Voltage), device contents are protected against program, erase, and block-lock operations. Numonyx StrataFlash Wireless Memory (L18/ L30) PROGRAM/ ERASE POWER: Valid V PP voltages allow block erase/ program functions. When V PP V PPLK (Lockout Voltage), device contents are protected against program, erase, and block-lock operations. Block erase and program at invalid V PP voltages should not be attempted Hardware Read-While-Write (RWW) The memory array of the L18/L30 device is divided into multiple partitions. This enables the device to perform simultaneous read-while-write (or erase) operations. Note, however, that reading and writing cannot be performed simultaneously in the same partition. Also, simultaneous program and erase is not allowed. Only one partition at a time can be in program or erase mode. Burst reads are allowed across partition boundaries. However, non-array read operations such as reading the Protection Register and CFI queries have special requirements with respect to simultaneous operation capability. Refer to the L18/L30 device datasheet for details. Application Note November Order Number:

13 4.1.7 Power and Voltage Regulation The L18/L30 device incorporates technology that enables low power designs. Designed for low-power systems, the L18/L30 device supports read, program, and erase operations at 1.8 volt V CC. Also, in addition to its low-current standby state (CE#-high), the L18/L30 device features an Automatic Power Saving mode, or APS. The L18/L30 device automatically enters APS following read-cycle completion. The L18/L30 device flash memory devices consume less power than K3/K18 flash memory during read cycles. Active read current is less because the L18/L30 device uses a lower core voltage, and senses fewer array cells than K3/K18 flash memory. The L18/L30 device programming and erasing currents are also lower than that of the K3/ K18 flash memory device. Worst-case peak currents for the L18/L30 device occur during read-while-write operations. This affects voltage-regulator requirements for the system s memory subsystem. System designers should also consider the following: 1.8 V core voltage (Vcc) operation High temperature effects Continuous read-while-write operation Standby current levels (Iccs) Active current levels (Iccr) Transient voltage/current peaks produced by falling and rising edges of CE# and OE# Program/ Erase Voltages When programming or erasing the L18/L30 flash memory device, a valid V PP voltage must be present on V PP. In addition to programming and erasing at 1.8 volt V CC, the L18/L30 device supports standard programing, Buffered Programming, and Buffered Enhanced Factory Programming (BEFP) modes. BEFP uses a V PP range of 8.5 V to 9.5 V, providing faster program and erase performance resulting in improved factory throughput. 4.2 Software Design Considerations This section describes software considerations when migrating from K3/K18 flash memory to the L18/L30 device Memory Partitioning The K3/K18 flash memory device is a single-partition device with its memory array organized into equal-size symmetrical blocks that are 64-KW each (see Figure 6, Memory Map - K3/K18 on page 14). The total number of blocks varies depending on the device s total density- the 64-Mbit device has 64 blocks, the 128-Mbit device has 128 blocks, and the 256-Mbit device has 256 blocks. November 2007 Application Note Order Number:

14 Figure 6: Memory Map - K3/K18 FFFFFF Block A MAX - A 17 Block Select A 16 - A 5 Row Select A 4 Group Select A 3 - A 1 Word Select 256-Mbit Device 128-Mbit Device 64-Mbit Device 7FFFFF 3FFFFF 3FFFF 2FFFF 1FFFF FFFF 0 Block Block Block 3 Block 2 Block 1 Block 0 64Mb A MAX = A Mb A MAX = A Mb A MAX = A 24 Each Block 64-Kword 16-words per Row 8-word Group 8-word Group 4K-rows per Block Unlike the K3/K18 flash memory device, the memory array of the 64-, and 128-Mbit L18/L30 device is divided into multiple 8-Mbit partitions- the 64-Mbit device has eight partitions, the 128-Mbit device has sixteen partitions. The 256-Mbit L18/L30 flash memory array is divided into multiple of 16-Mbit partitions - the 256-Mbit device has 16 partitions. Each device has one Parameter partition (top or bottom) and multiple Main partitions. The Parameter partition is organized as four 16-KWord parameter blocks and seven 64- KWord main blocks. Main partitions contain eight 64-KW main blocks each. The memory map for the top-parameter L18/L30 device is shown in Table 4 where the parameter partition is located at the highest physical address area. Table 6 shows the memory map for the bottom-parameter L18/L30 device where the parameter partition is located at the lowest physical address area. Application Note November Order Number:

15 Table 4: Top Parameter Memory Map - 64 and 128 Mbit Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit FC000-3FFFFF FC000-7FFFFF 8-Mbit Parameter Partition One Partition F8000-3FBFFF F8000-7FBFFF F4000-3F7FFF F4000-7F7FFF F0000-3F3FFF F0000-7F3FFF E0000-3EFFFF E0000-7EFFFF 8-Mbit Parameter Partition One Partition FFFF FFFF 8-Mbit Main Partition Seven FFFF 8-Mbit Main Fifteen FFFF FFFF FFFF Table 5: Top Parameter Memory Map Mbit Size (KW) Blk 256-Mbit FFC000-FFFFFF 16-Mbit Parameter Partition One Partition FF8000-FFBFFF FF4000-FF7FFF FF0000-FF3FFF FE0000-FEFFFF F00000-FFFFFF 16-Mbit Main Seven Eight EF0000-EFFFFF FFFF F0000-7FFFFF FFFF Table 6: Bottom Parameter Memory Map - 64 and 128 Mbit Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit November 2007 Application Note Order Number:

16 Table 6: Bottom Parameter Memory Map - 64 and 128 Mbit Size (KW) Blk 64-Mbit Size (KW) Blk 128-Mbit 8-Mbit Main 8-Mbit Parameter Partition Seven One Partition F0000-3FFFFF 8-Mbit Main Fifteen F0000-7FFFFF FFFF FFFF FFFF 8-Mbit Parameter Partition One Partition FFFF FFFF FFFF C000-00FFFF C000-00FFFF BFFF BFFF FFF FFF FFF FFF Table 7: Bottom Parameter Memory Map Mbit Size (KW) Blk 256-Mbit 16-Mbit Main 16-Mbit Parameter Partition Eight Seven One Partition FF0000-FFFFFF FFFF F0000-7FFFFF FFFF F0000-0FFFFF FFFF C000-00FFFF BFFF FFF FFF Device Identification As with the K3/K18 flash memory device, the L18/L30 device has its own unique device identification code. System software can be pre-enabled for the L18/L30 device by inserting conditional jumps to device-specific configuration routines based on the device ID code that is read during system initialization. Table 8 shows the device IDs available for the L18/L30 device. Application Note November Order Number:

17 Table 8: Device ID codes - L18/L30 Device Identifier Codes ID Code Type Device Address * Device Type Device Density T (Top Parameter) B (Bottom Parameter) Manufacturer Code 0x00 Numonyx Flash (V CC / V CCQ ) All 0089 Device Code 0x01 L18/L30 device 1.8V/ 1.8V L18/L30 device 1.8V/ 3.0V 64 Mbit 880B 880E 128 Mbit 880C 880F 256 Mbit 880D Mbit Mbit Mbit Note: * Numonyx reserves other locations within the Identifier address space for future use Read Configuration Register As with the K3/K18 flash memory, the Read Configuration Register (RCR) used on the L18/L30 device enables and configures synchronous burst- mode reads. The same device commands are used to write to, and read from, the RCR on the K3/K18 and the L18/L30 device. However, their register field values differ slightly. These differences are shown in Table 9. Table 9: Read Configuration Register Differences Register Field Value Numonyx Synchronous StrataFlash Memory (K3/K18) Numonyx StrataFlash Wireless Memory (L18/ L30) Latency Count (RCR[13:11]) Code 2 through Code 6 Available Latency Count (RCR[14:11]) Code 2 through Code 10 Available Burst Wrap (RCR[3]) 0 = Wrap burst within burst length 1 = Do not wrap within burst length (default to 0 ) Available Burst Length (RCR[2:0]) 001 = 4 word burst 111 = Continuous burst Reserved Available 4.3 Program/Erase Operations The L18/L30 device offers production program and erase voltage to enhance its performance. The production programming voltage range is higher than the K3/K18 flash memory device and available in standard word programming, Buffered Programming, and Buffered Enhanced Factory Programming (Buffered EFP) Factory Programming Voltage The L18/L30 device has a lower standard programming voltage than the K3/K18 flash memory device. However, the L18/L30 device also supports 9 volt factory programming higher than that offered on the K3/K18 flash memory device over its operating range (see Table 10). November 2007 Application Note Order Number:

18 Table 10: Programming Voltage Comparison Symbol Parameter Numonyx Synchronous StrataFlash Memory (K3/ K18) Numonyx StrataFlash Wireless Memory (L18/ L30) Unit Min Nom Max Min Nom Max T C Operating Temperature C V PPL V PP Voltage Supply (Logic Level) Standard V PPH1 Production Programming V PP V 4.4 Write State Machine Refer to the Next State Table of the Write State Machine described in the L18/L30 device datasheet for information regarding its read-while-write/erase dual-operation capabilities. 4.5 Program and Erase Characteristics Table 11 shows the L18/L30 device program and erase timing characteristics. Table 11: Program/Erase Characteristics - L18/L30 Number Symbol Parameter V PPL V PPH Units Min Typ Max Min Typ Max W200 t PROG/W Program Time Word Programming Single word 150 TBD 150 TBD Single cell 30 TBD 30 TBD Buffered Programming µs W200 t PROG/W Single word 150 TBD 150 TBD Program Time W251 t BUFF One Buffer (32 words) 640 TBD µs Buffered EFP W400 t BEFP/W Program Single word N/A N/A N/A N/A µs Erasing and Suspending W500 t ERS/PB 16-KWord Parameter W501 t ERS/MB Erase Time 64-KWord Main s W502 t ERS/MB 128-KWord Main W600 t SUSP/P Suspend Program suspend W601 t SUSP/E Latency Erase suspend µs W602 t ERS/SUSP Erase to Suspend Erase or Erase Resume command to Erase Suspend command µs 5.0 Design Tools The K3/K18 flash memory design tools include VHDL and Verilog bus functional models, as well as IBIS files. These tools are available on Numonyx s website, or they may be obtained by contacting an Numonyx field representative. Application Note November Order Number:

19 The L18/L30 device design tools include VHDL bus functional models and IBIS files. These tools can be obtained by contacting an Numonyx field representative. 5.1 Numonyx Flash Software Numonyx offers a variety of software solutions for its flash memory products. The following sections describe the available flash software Numonyx Flash Data Integrator Numonyx Flash Data Integrator (Numonyx FDI) is an Numonyx-supported code, data, and file manager for use in real-time embedded applications. Numonyx FDI's data manager component provides a simple storage API (application programmer interface) that makes it easy to replace EEPROM with flash memory. The data manager also includes a high-performance interface for streaming data in voice recording and multimedia applications, as well as packetized data. Numonyx FDI's code manager component allows for direct execution of code, including Java* applets and native CPU software. Numonyx FDI's file manager component presents a user-friendly ANSI-style interface for software developers, streamlining the development of data-centric applications. Numonyx FDI is founded upon robust power-loss recovery mechanisms, which ensure that data remains uncorrupted even through fluctuations and failure of power to the system. In addition, Numonyx FDI's intelligent wear-leveling techniques increase cycling endurance of flash memory blocks. Numonyx FDI's read-while-write (RWW) capabilities are optimized to allow data writes while simultaneously reading code from the same flash memory component. Numonyx FDI acts as a real-time interrupt handler, enabling software-based RWW. In software-based RWW, Numonyx FDI queues data to be written, while code runs directly out of flash memory; when code is not being read, Numonyx FDI performs flash write operations in the background to transfer queue contents to flash memory. When hardware-based RWW is available (as featured in the L18/L30 device), Numonyx FDI takes full advantage of the hardware features to reduce interrupt latency. Numonyx FDI comprehends all the available features of available flash memory. When an internal data buffer is present (such as with the L18/L30 device and the K3/ K18 flash memory device), Numonyx FDI optimizes write performance by storing data through the internal data buffer. Numonyx FDI also provides an interface for storing information in multiple User Protection Registers, or extended One-Time Programmable (OTP) bits. Finally, Numonyx FDI has full support for page and synchronous burst modes available in many flash memory devices Numonyx Persistent Storage Manager Numonyx Persistent Storage Manager (Numonyx PSM) software simplifies designs by combining all non-volatile memory functions into a single chip. Future versions of Numonyx PSM are planned that will provide reliable, cost-effective, high-density memory management for designs using the L18/L30 device. November 2007 Application Note Order Number:

20 Appendix A Additional Information Order/Document Number Document/Tool Numonyx Synchronous StrataFlash Flash Memory (K3/K18) Datasheet Numonyx StrataFlash Wireless Memory Datasheet (L18) Numonyx StrataFlash Wireless Memory Datasheet with 3 Volt I/O (L30) Numonyx Flash Memory Chip Scale Package User s Guide Numonyx Flash Data Integrator (FDI) User s Guide Numonyx Persistent Storage Manager User Guide Note: Contact your local Numonyx distribution sales office or visit Numonyx s World Wide Web home page at for technical documentation, tools, or for the most current information on Numonyx StrataFlash memory. Application Note November Order Number: