2/14/2016. Hardware Synthesis. Midia Reshadi. CE Department. Entities, Architectures, and Coding.
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1 Hardware Synthesis MidiaReshadi CE Department Science and research branch of Islamic Azad University Midia Reshadi 1 Chapter 2 Entities, Architectures, and Coding Styles Midia Reshadi 2 1
2 VHDL description entity declaration architecture body VHDL description An architecture body can be one of three basic coding styles: dataflow Behavioral structural. Midia Reshadi 3 Design Entity Design Units Library Units Entity declaration Architecture body Package declaration Package body Configuration declaration Midia Reshadi 4 2
3 Entity declaration entity half_adder is port (a, b : in std_logic; end half_adder; Midia Reshadi 5 Notation in syntax definitions Midia Reshadi 6 3
4 Default Port Mode Note in port (a, b : in std_logic; VHDL is not case sensitive Half_Adder= half_adder Midia Reshadi 7 Port s mode Mode linkage used to: link VHDL models with models written in other languages or to interface with non-vhdl simulators. Signal Sources output port carry_out is driven by the driver a and b carry_out <= a and b; Midia Reshadi 8 4
5 Port s mode Midia Reshadi 9 Architecture body An architecture body defines either the behavior or structure of a design entity architecture dataflow of half_adder is sum <= (not a and b) or (a and not b); carry_out <= a and b; end dataflow; Midia Reshadi 10 5
6 Coding Styles Basic coding styles Dataflow Behavioral, Structural A dataflow architecture uses only concurrent signal assignment statements. A behavioral architecture uses only process statements. A structural architecture uses only component instantiation statements. Midia Reshadi 11 Dataflow Style entity half_adder is port (a, b : in std_logic; end half_adder; architecture dataflow of half_adder is sum <= a xor b; Concurrent signal carry_out <= a and b; end dataflow; assignment statements Midia Reshadi 12 6
7 Behavioral Style Sequential statements like a conventional programming language entity half_adder is port (a, b : in std_logic; end half_adder; Midia Reshadi 13 Behavioral Style architecture behavior of half_adder is ha: process (a, b) if a = '1' then sum <= not b; carry_out <= b; else sum <= b; carry_out <= '0'; end if; end process ha; end behavior; Midia Reshadi 14 7
8 Structural Style XOR gate component entity xor_2 is -- Entity declaration for 2 input XOR gate port (i1, i2 : in std_logic; o1: out std_logic); end xor_2; architecture dataflow of xor_2 is -- Architecture body for 2 input XOR o1 <= i1 xor i2; end dataflow; Midia Reshadi 15 Structural Style AND gate component entity and_2 is -- Entity declaration for 2 input AND gate port (i1, i2 : in std_logic; o1: out std_logic); end and_2; architecture dataflow of and_2 is -- Architecture body for 2 input AND o1 <= i1 and i2; end dataflow; Midia Reshadi 16 8
9 Structural Style HALF-ADDER structure entity half_adder is -- Entity declaration for half adder port (a, b : in std_logic; end half_adder; architecture structure of half_adder is -- Architecture body for half adder u1: entity xor_2 port map (i1 => a, i2 => b, o1 => sum); u2: entity and_2 port map (i1 => a, i2 => b, o1 => carry_out); end structure; Midia Reshadi 17 Instantiation Midia Reshadi 18 9
10 Component instantiation u1: entity xor_2 port map (i1 => a, i2 => b, o1 => sum); Association symbol (connection) symbol ( => ) Midia Reshadi 19 Association Named Association u1: entity xor_2 port map (i2 => b, o1 => sum, i1 => a); Positional Association u1: entity xor_2 port map (a, b, sum); Based on relative positions as specified in the entity s declaration. Midia Reshadi 20 10
11 Components in VHDL Component Declarations component xor_2 port (i1, i2 : in std_logic; o1: out std_logic); end component; Component Instantiation u1: xor_2 port map (i1 => a, i2 => b, o1 => sum); Midia Reshadi 21 Components in VHDL Midia Reshadi 22 11
12 Components in VHDL entity half_adder is -- Entity declaration for half adder port (a, b : in std_logic; half_adder; end architecture structure of half_adder is -- Architecture body for half adder component xor_2 port (i1, i2 : in std_logic; o1: out std_logic); end component; component and_2 port (i1, i2 : in std_logic; o1: out std_logic); end component; -- xor_2 component declaration -- and_2 component declaration Midia Reshadi 23 Cont, u1: xor_2 port map (i1 => a, i2 => b, o1 => sum); u2: and_2 port map (i1 => a, i2 => b, o1 => carry_out); end structure; Midia Reshadi 24 12
13 Mixed Style entity half_adder is port (a, b : in std_logic; end half_adder; Midia Reshadi 25 Mixed Style architecture mixed of half_adder is Begin sum <= a xor b; -- dataflow concurrent statement co: process (a,b) -- start of process concurrent statement if a = '1' then carry_out <= b; else carry_out <= '0'; end if; end process co; -- end of process concurrent statement end mixed; Midia Reshadi 26 13
14 Synthesis results vscoding styles Dataflow style Midia Reshadi 27 Synthesis results vscoding styles Behavioral style Midia Reshadi 28 14
15 Synthesis results vscoding styles structural style Midia Reshadi 29 Synthesis results vscoding styles Technology dependent flattened-to-gates representation Midia Reshadi 30 15
16 Levels of abstraction Midia Reshadi 31 Design hierarchy Midia Reshadi 32 16
17 Design hierarchy Half-adder design entity entity half_adder is port (a, b : in std_logic; end half_adder; Midia Reshadi 33 Design hierarchy architecture dataflow of half_adder is sum <= a xor b; carry_out <= a and b; end dataflow; Midia Reshadi 34 17
18 Design hierarchy ---- Two input OR gate design entity entity or_2 is port (a, b : in std_logic; or_out : out std_logic); end or_2; architecture dataflow of or_2 is or_out <= a or b; end dataflow; Midia Reshadi 35 Design hierarchy Full-adder design entity entity full_adder is port (a, b, carry_in : in std_logic; end full_adder; architecture structure of full_adder is signal s1, s2, s3 : std_logic; -- Signals to interconnect components -- Each component instantion below is a concurrent statement ha1: entity half_adder port map (a => a, b => b, sum =>s1, carry_out => s2); ha2: entity half_adder port map (a => s1, b => carry_in, sum => sum, carry_out => s3); or1: entity or_2 port map (a => s3, b => s2, or_out => carry_out); end structure; Midia Reshadi 36 18
19 Top-level design entity library parts; use parts.all; Multiple Design File Description entity full_adder is port (a, b, carry_in : in std_logic; end full_adder; architecture structure of full_adder is signal s1, s2, s3 : std_logic; -- Signals to interconnect components ha1: entity half_adder port map (a => a, b => b, sum => s1, carry_out => s2); ha2: entity half_adder port map (a => s1, b => carry_in, sum => sum, carry_out => s3); or1: entity or_2 port map (a => s2, b => s3, or_out => carry_out); end structure; Midia Reshadi 37 Questions? MidiaReshadi 38 19
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