EX4 DIGITAL ELECTRONICS After completing the task and studying Unit 1.6, students will be able to: (check all that apply):

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1 EX4 DIGITAL ELECTRONICS G After completing the task and studying Unit 1.6, students will be able to: (check all that apply): Design and use standard combinational circuit building blocks: multiplexers (or data selectors), demultiplexers (or distributors), binary decoders and encoders, decoders for hexadecimal to sevensegment LED displays, code converters Design and use standard arithmetic combinational circuits: Arithmetic combinational modules and networks: 1bit half adder and full adder; ripplecarry and fast carrylookahead adder modules, adder and subtractor unit of signed integers in two s complement, overflow and zero detection capabilities, comparators, array multipliers for unsigned numbers, onedigit and larger BCD adders, parity generators and checkers, arithmetic logic units (ALU) Implement logic functions by the method of decoder Implement logic functions by the method of multiplexers (Shannon s Expansion Theorem) Plan and organise in the basic 3 blocks (input, output and control) an application project Apply the application project template for writing a quality document Capture a diagram schematic in ProteusVSM and run the simulation Produce a written solution for the exercise using the instructions from: Work cooperatively in a team of 3 members using the method described in: Write down the most significative doubts or questions you have had while or after completing the task: STATEMENT: My signature below indicates that I have (1) made equitable contribution to EX4 as a member of the group, (2) read and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3) acknowledged by name anyone outside this group who assisted this learning team or any individual member in completing this document. Today s date: Active members Roles: (reporter, simulator, etc.) (1) (2) (3) Acknowledgement of individual(s) who assisted this group in completing this document: (1) (2) Study time (in hours) Group Individual Student 1 Student 2 Student 3

2 Let s start the design of a digital clock... Planning the digital clock block diagram 1 First of all, explain the block diagram in Fig. 1, the keyboard circuit in Fig. 2, and the multiplexed display subsystem in Fig HOURS MINUTES SECONDS ENTER HS MS SS TS DIGITAL CLOCK ENTER_L F_L[3..0] L_L[6..0] COM[5..0] CLOCK Fig. 1 Input, output and control modules of the digital clock to be designed Designing the keyboard encoders We will have to produce 2 different encoders, one for the numeric data and another for the function keys. The additional ENTER key will validate the 2digits data input. Internal design of a standard block using logic gates 2 Implement a cascadable COD4:2 to encode the function keys in Fig. 2 using logic gates NOR. The block must have the input EI, and the outputs EO and GS. See Unit Use this block for the function keys encoder so that the outputs signal GS becomes GSF (group select function). Cascading standard blocks 3 Use the previously designed COD4:2 to produce the numeric keyboard encoder COD10:4 needed in Fig. 2 for encoding the number keys. Group select data output (GSD) is high when any numeric key is pressed. Compare your design with the one you will obtain when using chips 74LS148 or 74LS K_L0 K_L1 K_L2 5 6 K_L4 K_L5 K_L6 9 7 K_L8 K_L9 K_L3 K_L7 NUMERIC KEYBOARD HS MS SS F_L0 F_L1 F_L2 TS F_L3 CODI[3..0] GS NUM_KEY FUNCTION KEYBOARD COD[3..0] GSD ENTER KEY F_L[3..0] VCC CODI[1..0] K_L[3..0] GS FUNCT_KEY FC[1..0] GSF 10k ENTER Fig. 2 Keyboard and buttons for operating the clock

3 Designing the display subsystem A multiplexed display system will be planned and designed for representing up to 6 hexadecimal digits. Implementing logic functions using the method of decoders 4 Deduce the truth table for an activelow (for common anode) hexadecimal to 7segment display decoder (HEX7SEG) and implement it using the method of decoders Using standard MSI chips 5 Implement the DECDIGIT module in Fig. 3 using an standard TTL decoder like the 74LS138 Implementing logic functions using the method of multiplexers 6 For example, each member of the cooperative group can implement one of the outputs Y0_L, Y1_L, and Y2_L of the DECDIGIT module in Fig. 3, using the method o multiplexers and a MU (or a MUX4, or a MUX8, or a MU6). Discuss the drawbacks of the multiplexer s method if many outputs have to be implemented and compare with the advantages of the decoder s method. Cascading standard blocks 7 Produce the multiplexed display driver in Fig. 3 using the previous HEX7SEG module and cascading MU. Remember: plan a block diagram with the big entities and the interconnection; implement and verify by simulation each entity separately. E DEC_DIGIT E DEC_DIGIT Y5_L Y4_L Y3_L Y2_L Y1_L Y0_L R1 1k B5 B4 B3 B2 B1 BO B[5..0] VCC B5 Q6 B4 Q5 B3 Q4 B2 Q3 B1 Q2 B0 Q1 HOURS MINUTES MUX 7SEG DRIVER SECONDS HT[3..0] TT[3..0] TH[3..0] H[3..0] T[3..0] U[3..0] HT[3..0] TT[3..0] TH[3..0] H[3..0] T[3..0] U[3..0] a_l b_l c_l d_l e_l f_l g_l DISPLAY_DRIVER R Fig. 3 6digit multiplexed 7segment display subsystem

4 Let s start your application project Choose a title for the application project you want to develop 2. Read the application project documentation template found in 3. Design the general block diagram clearly specifying the input and output combinational subsystems and the control block 4. Design the combinational blocks of your project considering what you have learned from E to EX4

5 DIGITAL ELECTRONICS G Working plan 1 for solving the exercise EX Explain succinctly how the cooperative group has organize the realization of the exercise: i.e., which has been your working plan; in which way has you divided the task fairly so that more or less all of you are doing a similar amount of work; how have you learned each other s materials; what has been worked out in class time (sessions A and B) and what has been resolved in sessions C; and so on... white down also your impressions or opinions about how your group work is going 2... Active members signatures 1 This document, filled before delivering the exercise, will be included in the group learning portfolio 2 Check similar documents in and

Chapter 4. Combinational Logic

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