קורס VHDL for High Performance. VHDL
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1 קורס VHDL for High Performance תיאור הקורס קורסזהמספקאתכלהידע התיאורטיוהמעשילכתיבתקודHDL. VHDL לסינתזה בעזרת שפת הסטנדרט הקורסמעמיקמאודומלמדאת הדרךהיעילהלכתיבתקודVHDL בכדילקבלאתמימושתכןהלוגי המדויק. הקורסמשלב 50% תיאוריהו- 50% עבודהמעשיתבכלמפגש. המעבדותמכסותאתכלהחומר התאורטיומשלבות חשיבהותכנוןדיגיטאלימעשי. הקורסמשדרגגםמהנדסים עםהרבהשנותניסיוןבתחום. הקורסמכסהאתתהליךהסינתזהבמלואוהחלמהמתודולוגיה, כליהפיתוח, הכנסת,CONSTRAINTS מימושכלמבנה VHDL בצורהאופטימאלית, הבנתהבעיותעםסגנוןכתיבהלא מדויק, הבדליםבין סימולציהלפניואחריסינתזה, ניתוח מסלוליםקריטיים, קריאה וניתוחדו"חות. בנוסףהקורסמעמיקבכתיבת קודיעיללחיסכוןבמקום, הגדלתהתדר, תכנוןלהספקנמוך, בעיות שלSKEW, עבודהעםIP חיצוניים,שימושב- ATTRIBUTES, מימוש מכונותמצביםעםאמינותגבוהה אולתדרגבוה, פתרוןבעיות.FANOUT אורך הקורס 5 ימים (אופציהל- 6 ימיםעםעבודהמעשיתעל (ALTERA DE2-115 EVM בסיום הקורס מטרות שיושגו הכרתתהליךהסינתזהוההבדלבין כליפיתוחשונים כתיבהמדויקתשלמעגלים קומבינטוריםומעגליםעםשעון תכנוןלסינתזהשלפרויקטמרובהקבצים הכרהוהכנסתאילוצים (CONSTRAINTS) הכרתהבעיותבכתיבהלאמדויקת, בעיותבסימולציה אחריסינתזה תכנוןיעיל לחיסכוןבמקוםאולתדרגבוה עבודהעם IP ושילובובתהליךהסינתזה הפקהוניתוחדו"חות, זיהויותיקוןבעיותשל TIMING אוכלוסיית היעד מהנדסיחומרה אותוכנההעובדיםבפיתוח FPGA ומעונייניםלשדרגאתיכולותיהם, להכיראת מגבלותכליהסינתזה, להביןטוביותר כיצדלהימנעמתקלותוכיצדלכתוב קודיעיללסינתזה.
2 כלי פיתוח בקורס סימולטור HDL) (Modelsim or Active סינטיסייזר Pro) (Quartus II integrated synthesis, Precision or Synplify לוחפיתוחשלחברתALTERA (אופציונאליבעלותנוספת) תכנית הלימוד Introduction to Synthesis Day #1 o The synthesis process Technology library Constraint HDL files Compiler Mapping Generated Netlist o Hardware inference versus hardware instantiation o Simulation versus Synthesis Concurrent Signal Assignment Synthesis o General guidelines Data types Initialization of signals Operand length o Inference from declarations Integer State machine std_logic_vector Other data types o Inference from Z value tri-state buffer Bi-Directional I/O tri-state MUX tri-state buffer bus o Inference from simple concurrent signal assignment Logical operator
3 RTL and Technology view analysis Using synthesizer attributes Closed feedback loop problem o Inference from conditional signal assignments WHEN-ELSE synthesis LUT equation analysis UNAFFECTED key word LATCH problem Don t care in synthesis std_match function WITH-SELECT synthesis o Inference from arithmetic and relational operators Integer versus REAL Arithmetic operators: +, -, *, /, abs, ** Relational operators: >, <, =, /=, >=, <= Constants in arithmetic and relational operators o Simulation versus synthesis behavior and synthesis guidelines Operator Sharing o Derivation of efficient HDL description o Reducing circuit size o Operator sharing using VHDL description o Operator sharing using synthesizer GUI options o Analyzing area and frequency o Tradeoff analysis o Complex operator sharing and synthesis tools limitations
4 Day #2 Sequential Statements Synthesis o Inference from within processes introduction o General guidelines Using variables Case versus IF-ELSE Combinational sensitivity list Sequential sensitivity list o Inference from simple assignment statements Signals versus Variables synthesis o Inference from IF-THEN-ELSE and IF-THEN-ELSIF statements Priority Latch problem Full versus partial sensitivity list Combinational versus sequential If statements Variables versus Signals synthesis Operator sharing within process Nested IF statements synthesis Analyzing results on different synthesizers o Inference from Case statements When-Others statement synthesis Combinational versus sequential sensitivity list Null key word Latch problem Don t care in Case statements o Inference from loop statements Serial loop versus parallel loop synthesis Loop index FOR loop versus while and simple loop synthesis Variables versus Signals in loop synthesis o Combinational circuit design examples Gray code incrementor Programmable priority encoder Signed addition with status Combinational adder based multiplier Hamming distance circuit
5 Day #3 Sequential Statements Synthesis (continue) o Incomplete Sensitivity List Bad versus good coding style, simulation pre and post synthesis o Inference using Variables Versus Signals variables and signals in combinational processes, variables and signals in sequential processes, when variable becomes register, analyzing synthesis warnings, debugging variables in post synthesis simulation o Synchronous Circuits Inference latch versus flip-flop inference Synchronous and asynchronous reset Load and enable signals o Inference from WAIT Statements Combinational WAIT processes Sequential WAIT processes Non synthesizable WAIT statements Variables versus signals in WAIT statements Synchronous reset in WAIT statements Finite State Machine Synthesis o State machine structure (Mealy and Moore block diagram) o State encoding (Auto, one-hot, binary, Johnson, two-hot, Gray, User specific) o State machine implementation in VHDL (one, two or three processes) o Bad coding style for state machine o Specifying encoding style in VHDL and in synthesizer tool o Analyzing encoding style area and performance o High reliability safe state machines using attributes, handling illegal states
6 Day #4 Timing Analysis of a Synchronous Sequential Circuits o Introduction to timing constraints and synchronous design techniques o Synchronized versus unsynchronized I/O o Setup time violation and maximal clock rate o Synthesis static analysis formula o Hold time violation o Output related timing considerations o Input related timing considerations o Poor design practices and their remedies Misuse of asynchronous signals Misuse of gated clock Misuse of derived clocks Global clock Clock skew o Analyzing critical paths in details o Synthesis static timing analysis versus Place & Route static timing analysis o Fanout and long combinational chain timing problems o Using PLL in the system o Physical Synthesis versus logical synthesis Day #5 Synthesis of Large Projects o Synthesis of Package & Package Body o Synthesis of functions & procedures o Reuse methodology o Synthesis of IEEE packages Integrating IP Core o IP core generation and integration into VHDL code o IP black box constraints Maximize Clock Rate
7 o Introduction to pipeline o Latency and throughput o Pipelined combinational circuits o Pipelining considerations o Pipeline balancing o Effectiveness of pipeline o Adding a pipeline in VHDL o Analyze clock rate in pipelined design o Complex pipeline circuits o Retiming Day #6 (optional) Practical exercises on ALTERA EVM o Description of evaluation board main components o Programmer configuration o Seven segment and LED exercises o Counters, PLL,clock switch on the fly o External memory interface o Timing analysis with TimeQuest o Place & Route process o Pins configuration
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