Programmable Logic Devices UNIT II DIGITAL SYSTEM DESIGN

Transcription

1 Programmable Logic Devices UNIT II DIGITAL SYSTEM DESIGN

2 2

3 3

4 4

5 5

6 6

7 7

8 8

9 9

10

11

12 2

13 3

14 4

15 5

16 6

17 7

18 8

19 9

20 2

21 Implementation in Sequential Logic 2

22 PAL Logic Implementation Design Example: BCD to Gray Code Converter A B Truth Table C D W X X X X X X X X X X X X X Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D Y X X X X X X Z X X X X X X C AB CD B A X X X X X X K-map for W A AB CD C X X X X X X B K-map for Y K-maps D D C AB CD B A X X X X X X K-map for X A AB CD C X X X X X X B K-map for Z D D 22

23 CLK D Q Q N Seq D Q Q D Seq D Q Open Reset Com 23

24 PLD (Programmable Logic Device) All layers already exist Designers can purchase an IC Connections on the IC are either created or destroyed to implement desired functionality Field-Programmable Gate Array (FPGA) very popular Benefits Low NRE costs, almost instant IC availability Drawbacks Bigger, expensive (perhaps $3 per unit), power hungry, slower Vahid & Givargis 24

25 Speed Flexibility Comparison Technology Performance/ Cost Time until running Time to high performance Time to change code functionality ASIC Very High Very Long Very Long Impossible FPGA Medium Medium Long Medium ASIP/ DSP High Long Long Long Generic Low-Medium Very Short Not Attainable Very Short 25

26 Roadmap PROM PLA PAL CPLD FPGA 26

27 PLD Definition Programmable Logic Device (PLD): An integrated circuit chip that can be configured by end use to implement different digital hardware Also known as Field Programmable Logic Device (FPLD) 27

28 PLD Advantages Short design time Nonrecurring engineering cost Less expensive at low volume PLD ASIC Volume 28

29 PLD Categorization PLD SPLD Simple PLD HCPLD High Capacity PLD PLA PAL Programmable Array Logic CPLD Complex PLD FPGA Field Programmable Gate Array 29

30 Programmable ROM (PROM) N input 2 N x M ROM M output Address: N bits; Output word: M bits ROM contains 2 N words of M bits each The input bits decide the particular word that becomes available on output lines 3

31 Logic Diagram of 8x3 PROM Sum of minterms 3

32 Combinational Circuit Implementation using PROM I I I2 F F F2 F F F2 32

33 PROM Types Programmable PROM Break links through current pulses Write once, Read multiple times Erasable PROM (EPROM) Program with ultraviolet light Write multiple times, Read multiple times Electrically Erasable PROM (EEPROM)/ Flash Memory Program with electrical signal Write multiple times, Read multiple times 33

34 PROM: Advantages and Disadvantages Widely used to implement functions with large number of inputs and outputs Design of control units (Micro-programmed control units) For combinational circuits with lots of don t care terms, PROM is a wastage of logic resources 34

35 Programmable Logic Array n x k links k AND gates k X m links m OR gates m outputs n inputs n x k links Programmable AND array + programmable OR array n x k x m PLA has 2n x k + k x m links Sum of products 35

36 PLA 4 X 6 X 2 36

37 Logic Implementation with PLA Finite number of AND gates => simplify function to minimum number of product terms Number of literals in a product term is not important since we have all the input variables Sharing of product terms between outputs => multiple-output minimization 37

38 Design with PLA 38

39 Programmable Array Logic (PAL) Programmable AND array Fixed OR array Each output line permanently connected to a specific set of product terms Number of switching functions that can be implemented with PAL are more limited than PROM and PLA 39

40 PAL Logic Diagram 4

41 PAL Implications Number of product terms per output > number of product terms in each sum-ofproduct expression No sharing of product terms between outputs 4

42 Design with PAL 42

43 Complex Programmable Logic Devices Complex PLDs typically combine PAL combinational logic with FFs Organized into logic blocks Fixed OR array size Combinational or registered output Some pins are inputs only Usually enough logic for simple counters, state machines, decoders, etc. e.g. GAL22V, GAL6V8, etc. 43

44 GAL CPLD OLMC (Output Logic MacroCell) has OR, FF, output multiplexer and I/O control logic. Note that OLMC output is fed back to input matrix for use in other OLMCs. 44

45 Programmable Interconnect CPLD Logic Block Logic Block I/O I/O Logic Block Logic Block 45

46 CPLD Logic Block Simple PLD Inputs Product-term array Product term allocation function Macro-cells (registers) Logic blocks executes sum-of-product expressions and stores the results in micro-cell registers Programmable interconnects route signals to and from logic blocks 46

47 Major CPLD Resources Number of macro-cells per logic block Number of inputs from programmable interconnect to logic block Number of product terms in logic block 47

48 Structure of FPGA (Xilinx) Logic Block I/O Block Interconnect 48

49 Configurable Logic Block CLB 49

50 Logic Function Implemented as look-up table (LUT) K-input LUT corresponds to 2 K x bit memory K-input LUT can implement any k-input - output logic function 5

51 Configuring FPGA Configure CLB and IOB Configure interconnect Interconnect technology SRAM Anti-fuse (program once) EPROM / EEPROM 5

52 Programming Technology Name Re-programmable Volatile EPROM yes (out of circuit) no EEPROM yes (in circuit) no SRAM yes (in circuit) yes Antifuse no no 52

53 FPGA Applications Glue Logic (replace SSI and MSI parts) Rapid turnaround Prototype design Emulation Custom computing Dynamic reconfiguration 53