Enhancing Concurrency in Distributed Transactional Memory through Commutativity
|
|
- Frederick McKenzie
- 5 years ago
- Views:
Transcription
1 Enhancing Concurrency in Distributed Transactional Memory through Commutativity Junwhan Kim, Roberto Palmieri, Binoy Ravindran Virginia Tech USA
2 Lock-based concurrency control has serious drawbacks Coarse grained locking Simple But no concurrency
3 Fine-grained locking is better, but Excellent performance Poor programmability Lock problems don t go away! Deadlocks, livelocks, lock-convoying, priority inversion,. Most significant difficulty composition
4 Transactional memory Like database transactions ACI properties (no D) Easier to program Composable First HTM, then STM, later HyTM M. Herlihy and J. B. Moss (1993). Transactional memory: Architectural support for lock-free data structures. ISCA. pp N. Shavit and D. Touitou (1995). Software Transactional Memory. PODC. pp
5 Optimistic execution yields performance gains at the simplicity of coarse-grain, but no silver bullet Time Coarse-grained locking STM Fine-grained locking High data dependencies Irrevocable operations Interaction between transactions and non-transactions Conditional waiting Threads E.g., C/C++ Intel Run-Time System STM (B. Saha et. al. (2006). McRT- STM: A High Performance Software Transactional Memory. ACM PPoPP)
6 Contention management. Which transaction to abort? T0! T1!!! x = x + y;!!!!! x = x / 25;! x = x / 25;! Contention manager Can cause too many aborts, e.g., when a long running transaction conflicts with shorter transactions An aborted transaction may wait too long Transactional scheduler s goal: minimize conflicts (e.g., avoid repeated aborts)
7 Distributed TM (or DTM) Extends TM to distributed systems Nodes interconnected using message passing links Execution and network models Execution models Ø Data flow DTM (DISC 05) p p Transactions are immobile Objects migrate to invoking transactions Ø Control flow DTM (USENIX 12) p p Objects are immobile Transactions move from node to node Herlihy s metric-space network model (DISC 05) Ø Communication delay between every pair of nodes Ø Delay depends upon node-to-node distance ms ms ms ms ms 1st hop 2nd hop 3rd hop 4th hop 5th hop Distance
8 Paper s motivation How to boost transactions processing in DTM Read/Read No conflict Conflict! Write/Write Read/Write conflicts minimized thanks to the multi-versioning support
9 How? How can a concurrency control manager allow write conflicting transactions to commit concurrently without affecting isolation/consistency? Exploiting commutable operations
10 Commutable operations by examples (Data Structures) Thread1: Insert(2) Thread2: Insert(0) NON COMMUTABLE
11 Commutable operations by examples (Data Structures) Thread1: Insert(2) Thread2: Insert(5) COMMUTABLE
12 Commutable operations by examples (TPC-C) New Order transactions: Read: Ø Customer, District, Warehouse, Item, Stock Write: Ø District, Stock Payment: Read: Ø Warehouse, Customer, District Write: New Order Transactions: Write Ø district.d_next_o_id() Ø Payment Transactions: Write Ø district.d_ytd() Ø Ø Warehouse, Customer, District
13 Paper s contribution MV-TFA, a multi-versioned version of TFA (Transactional Forwarding Algorithm) ensuring Snapshot Isolation Read transactions don t abort CRF - Commutative Request First: a distributed transactional scheduler integrated with MV-TFA CRF assumes definition of commutable rules by programmer; Minimize abort rate Increase concurrency Increase performance Implementation and extensive experimental evaluation Comparisons with state-of-the art DTMs Experiments for the best tuning of the system
14 MV-TFA READ N0 - T1 N1- Owner O 1 N2 - Owner O 2 N3 - T3 Read (O 1 ) Object (O 10 ) Write(O 2 ) Object (O 21 ) Validate (O 2 ) OK(O 21 ) Commit (O 21 ) CH Ow (O 20, O 21 ) Read (O 2 ) Object(O 20 )
15 CRF WRITE without concurrent validations N1/Owner O 1 N0/T1 {[T1;X]} {[T2;X]} N4/T2 Write (O 1, [X]) Object (O 1 ) NON COMMUTABLE Write(O 1, [X]) Object (O 11 ) Validate (O 1 ) OK(O 11 ) Abort Commit (O 1 ) Restart
16 CRF WRITE with concurrent validations N1/Owner O 1 N0/T1 {[T1;X]} {[T2;X]} N4/T2 Write (O 1, [X]) COMMUTABLE Object (O 1 ) Validate (O 1 ) OK(O 1 ) Write(O 1, [Y]) Object (O 1 ) Validate (O 1 ) OK(O 1 ) Commit (O 1 ) Commit (O 1 )
17 CRF WRITE with concurrent validations N0/T1 N1/Owner O 1 {[T1;X]}{[T2;Y]}{[T3;Y]} Write (O 1, [X]) Object (O 1 ) Validate (O 1 ) OK(O 1 ) Write(O 1, [Y]) Object (O 1 ) Validate (O 1 ) OK(O 1 ) Commit (O 1 ) Commit (O 1 ) N4/T2 Write(O 1, [Y]) Object (O 1 ) Validate (O 1 ) Abort N5/T3 COMMUTABLE NON COMMUTABLE Restart
18 Depth of validation (MaxD) Transaction commit phase is stretched depending on the concurrent validating transactions Depth of validation (MaxD): the number of transactions involved in the validation N1/Owner O 1 N0/T1 {[T1;X]} {[T2;X]} N4/T2 Write (O 1, [X]) Object (O 1 ) Write(O 1, [Y]) Object (O 1 ) T 2$ validates$o 1.$ Epoch$of$Valida!on$!me$ Depth$$ of$valida!on$ Validate (O 1 ) Validate (O 1 ) OK(O 1 ) T 3$ validates$o 1.$ T 4$ validates$o 1.$ OK(O 1 ) Commit (O 1 ) Commit (O 1 )
19 Epochs CRF prioritizes commutable transactions for increasing concurrency. However adverse schedules can penalize non-commutable transactions CRF defines execution epochs: In each epoch, commutative transactions concurrently participate in validation. In the next epoch, the non-commutative transactions stored in the scheduling queue restart and validate Epoch shift is triggered when MaxD is reached or commitment process ends
20 Experiments Test-bed: Cluster of 10 nodes interconnected by a Gigabit connection Each node equipped with 12 cores 2 up to 120 concurrent threads in the system Competitors: DecentSTM, MV-TFA (without scheduling) Benchmarks: Micro Benchmarks: Ø Linked-List, Skip-list. Both implementation of Commutable Set Macro Benchmarks: Ø TPC-C. Field-based commutativity
21 Finding depth of validation Run experiments measuring the performance of the system varying the depth of validation parameter Threshold Threshold Linked List Max Depth = 10 TPC-C Max Depth = 5
22 Linked List Linkedlist(CRF-MV-TFA), 10% Read Linkedlist(MV-TFA), 10% Read Linkedlist(DcentSTM), 10% Read 1 thread 2 threads 4 threads 6 threads 8 threads 12 threads 500 (a) CRF-MV-TFA, 10% Read 500 (b) MV-TFA, 10% Read 500 (c) DecentSTM, 10% Read Linkedlist(CRF-MV-TFA), 90% Read Linkedlist(MV-TFA), 90% Read Linkedlist(DcentSTM), 90% Read 1 thread 2 threads 4 threads 6 threads 8 threads 12 threads 500 (d) CRF-MV-TFA, 90% Read (e) MV-TFA, 90% Read (f) DecentSTM, 90% Read
23 Skip List Skiplist(CRF-MV-TFA), 10% Read Skiplistlist(MV-TFA), 10% Read Skiplist(Decent), 10% Read thread 2 threads 4 threads 6 threads 8 threads 12 threads (a) CRF-MV-TFA, 10% Read (b) MV-TFA, 10% Read (c) DecentSTM, 10% Read Skiplist(CRF-MV-TFA), 90% Read Skiplist(MV-TFA), 90% Read Skiplist(Decent), 90% Read thread 2 threads 4 threads 6 threads 8 threads 12 threads (d) CRF-MV-TFA, 90% Read (e) MV-TFA, 90% Read (f) DecentSTM, 90% Read
24 TPC-C % of transaction profiles as in the original specification # warehouse = 4 to increase the conflict probability TPC-C(CRF-MV-TFA) TPC-C(MV-TFA) TPC-C(DecentSTM) thread 2 threads 4 threads 6 threads 8 threads 12 threads (a) CRF-MV-TFA (b) MV-TFA (c) DecentSTM
25 Thank you! Questions?
Scheduling Transactions in Replicated Distributed Transactional Memory
Scheduling Transactions in Replicated Distributed Transactional Memory Junwhan Kim and Binoy Ravindran Virginia Tech USA {junwhan,binoy}@vt.edu CCGrid 2013 Concurrency control on chip multiprocessors significantly
More informationLock vs. Lock-free Memory Project proposal
Lock vs. Lock-free Memory Project proposal Fahad Alduraibi Aws Ahmad Eman Elrifaei Electrical and Computer Engineering Southern Illinois University 1. Introduction The CPU performance development history
More informationDistributed Transactional Contention Management as the Traveling Salesman Problem
Distributed Transactional Contention Management as the Traveling Salesman Problem Bo Zhang, Binoy Ravindran, Roberto Palmieri Virginia Tech SIROCCO 204 Lock-based concurrency control has serious drawbacks
More informationScheduling Memory Transactions in Distributed Systems
Scheduling Memory Transactions in Distributed Systems Junwhan Kim Preliminary Examination Proposal Submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment
More informationEnhancing Concurrency in Distributed Transactional Memory through Commutativity
Enhancing Concurrency in Distributed Transactional Memory through Commutativity Junwhan Kim, Roberto Palmieri, and Binoy Ravindran ECE Department, Virginia Tech, Blacksburg, VA, 24061 {junwhan, robertop,
More informationScheduling Memory Transactions in Distributed Systems
Scheduling Memory Transactions in Distributed Systems Junwhan Kim Dissertation Submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements
More informationAutomated Data Partitioning for Highly Scalable and Strongly Consistent Transactions
Automated Data Partitioning for Highly Scalable and Strongly Consistent Transactions Alexandru Turcu, Roberto Palmieri, Binoy Ravindran Virginia Tech SYSTOR 2014 Desirable properties in distribute transactional
More informationChí Cao Minh 28 May 2008
Chí Cao Minh 28 May 2008 Uniprocessor systems hitting limits Design complexity overwhelming Power consumption increasing dramatically Instruction-level parallelism exhausted Solution is multiprocessor
More informationSoftware transactional memory
Transactional locking II (Dice et. al, DISC'06) Time-based STM (Felber et. al, TPDS'08) Mentor: Johannes Schneider March 16 th, 2011 Motivation Multiprocessor systems Speed up time-sharing applications
More informationHydraVM: Mohamed M. Saad Mohamed Mohamedin, and Binoy Ravindran. Hot Topics in Parallelism (HotPar '12), Berkeley, CA
HydraVM: Mohamed M. Saad Mohamed Mohamedin, and Binoy Ravindran Hot Topics in Parallelism (HotPar '12), Berkeley, CA Motivation & Objectives Background Architecture Program Reconstruction Implementation
More informationTRANSACTION MEMORY. Presented by Hussain Sattuwala Ramya Somuri
TRANSACTION MEMORY Presented by Hussain Sattuwala Ramya Somuri AGENDA Issues with Lock Free Synchronization Transaction Memory Hardware Transaction Memory Software Transaction Memory Conclusion 1 ISSUES
More informationSupporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication
Supporting Software Transactional Memory in Distributed Systems: Protocols for Cache-Coherence, Conflict Resolution and Replication Bo Zhang Dissertation Submitted to the Faculty of the Virginia Polytechnic
More informationTransactional Memory: Architectural Support for Lock-Free Data Structures Maurice Herlihy and J. Eliot B. Moss ISCA 93
Transactional Memory: Architectural Support for Lock-Free Data Structures Maurice Herlihy and J. Eliot B. Moss ISCA 93 What are lock-free data structures A shared data structure is lock-free if its operations
More informationIntegrating Transactionally Boosted Data Structures with STM Frameworks: A Case Study on Set
Integrating Transactionally Boosted Data Structures with STM Frameworks: A Case Study on Set Ahmed Hassan Roberto Palmieri Binoy Ravindran Virginia Tech hassan84@vt.edu robertop@vt.edu binoy@vt.edu Abstract
More information1 Publishable Summary
1 Publishable Summary 1.1 VELOX Motivation and Goals The current trend in designing processors with multiple cores, where cores operate in parallel and each of them supports multiple threads, makes the
More informationOn Improving Transactional Memory: Optimistic Transactional Boosting, Remote Execution, and Hybrid Transactions
On Improving Transactional Memory: Optimistic Transactional Boosting, Remote Execution, and Hybrid Transactions Ahmed Hassan Preliminary Examination Proposal submitted to the Faculty of the Virginia Polytechnic
More informationHyflowCPP: A Distributed Transactional Memory framework for C++
HyflowCPP: A Distributed Transactional Memory framework for C++ Sudhanshu Mishra Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the
More informationAn Automated Framework for Decomposing Memory Transactions to Exploit Partial Rollback
An Automated Framework for Decomposing Memory Transactions to Exploit Partial Rollback Aditya Dhoke Virginia Tech adityad@vt.edu Roberto Palmieri Virginia Tech robertop@vt.edu Binoy Ravindran Virginia
More information6.852: Distributed Algorithms Fall, Class 20
6.852: Distributed Algorithms Fall, 2009 Class 20 Today s plan z z z Transactional Memory Reading: Herlihy-Shavit, Chapter 18 Guerraoui, Kapalka, Chapters 1-4 Next: z z z Asynchronous networks vs asynchronous
More informationOn Open Nesting in Distributed Transactional Memory
Systor 12 On Open Nesting in Distributed Transactional Memory Alexandru Turcu Virginia Tech talex@vt.edu Binoy Ravindran Virginia Tech binoy@vt.edu Abstract Distributed Transactional Memory (DTM) is a
More informationThe Common Case Transactional Behavior of Multithreaded Programs
The Common Case Transactional Behavior of Multithreaded Programs JaeWoong Chung Hassan Chafi,, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun Computer Systems Lab
More informationTransactional Memory
Transactional Memory Architectural Support for Practical Parallel Programming The TCC Research Group Computer Systems Lab Stanford University http://tcc.stanford.edu TCC Overview - January 2007 The Era
More informationUsing Software Transactional Memory In Interrupt-Driven Systems
Using Software Transactional Memory In Interrupt-Driven Systems Department of Mathematics, Statistics, and Computer Science Marquette University Thesis Defense Introduction Thesis Statement Software transactional
More informationOn Developing Optimistic Transactional Lazy Set
On Developing Optimistic Transactional Set [Technical Report] Ahmed Hassan, Roberto Palmieri, Binoy Ravindran Virginia Tech {hassan84;robertop;binoy}@vt.edu Abstract. Transactional data structures with
More informationCost of Concurrency in Hybrid Transactional Memory. Trevor Brown (University of Toronto) Srivatsan Ravi (Purdue University)
Cost of Concurrency in Hybrid Transactional Memory Trevor Brown (University of Toronto) Srivatsan Ravi (Purdue University) 1 Transactional Memory: a history Hardware TM Software TM Hybrid TM 1993 1995-today
More informationOn Open Nesting in Distributed Transactional Memory
1 On Open Nesting in Distributed Transactional Memory Alexandru Turcu, Roberto Palmieri and Binoy Ravindran Abstract Distributed Transactional Memory (DTM) is a recent but promising model for programming
More informationPerformance Comparison of Various STM Concurrency Control Protocols Using Synchrobench
Performance Comparison of Various STM Concurrency Control Protocols Using Synchrobench Ajay Singh Dr. Sathya Peri Anila Kumari Monika G. February 24, 2017 STM vs Synchrobench IIT Hyderabad February 24,
More information6 Transactional Memory. Robert Mullins
6 Transactional Memory ( MPhil Chip Multiprocessors (ACS Robert Mullins Overview Limitations of lock-based programming Transactional memory Programming with TM ( STM ) Software TM ( HTM ) Hardware TM 2
More informationTransactional Memory. How to do multiple things at once. Benjamin Engel Transactional Memory 1 / 28
Transactional Memory or How to do multiple things at once Benjamin Engel Transactional Memory 1 / 28 Transactional Memory: Architectural Support for Lock-Free Data Structures M. Herlihy, J. Eliot, and
More informationMohamed M. Saad & Binoy Ravindran
Mohamed M. Saad & Binoy Ravindran VT-MENA Program Electrical & Computer Engineering Department Virginia Polytechnic Institute and State University TRANSACT 11 San Jose, CA An operation (or set of operations)
More informationLow Overhead Concurrency Control for Partitioned Main Memory Databases. Evan P. C. Jones Daniel J. Abadi Samuel Madden"
Low Overhead Concurrency Control for Partitioned Main Memory Databases Evan P. C. Jones Daniel J. Abadi Samuel Madden" Banks" Payment Processing" Airline Reservations" E-Commerce" Web 2.0" Problem:" Millions
More informationLecture 21: Transactional Memory. Topics: consistency model recap, introduction to transactional memory
Lecture 21: Transactional Memory Topics: consistency model recap, introduction to transactional memory 1 Example Programs Initially, A = B = 0 P1 P2 A = 1 B = 1 if (B == 0) if (A == 0) critical section
More informationMutex Locking versus Hardware Transactional Memory: An Experimental Evaluation
Mutex Locking versus Hardware Transactional Memory: An Experimental Evaluation Thesis Defense Master of Science Sean Moore Advisor: Binoy Ravindran Systems Software Research Group Virginia Tech Multiprocessing
More informationINTRODUCTION. Hybrid Transactional Memory. Transactional Memory. Problems with Transactional Memory Problems
Hybrid Transactional Memory Peter Damron Sun Microsystems peter.damron@sun.com Alexandra Fedorova Harvard University and Sun Microsystems Laboratories fedorova@eecs.harvard.edu Yossi Lev Brown University
More informationMcRT-STM: A High Performance Software Transactional Memory System for a Multi- Core Runtime
McRT-STM: A High Performance Software Transactional Memory System for a Multi- Core Runtime B. Saha, A-R. Adl- Tabatabai, R. Hudson, C.C. Minh, B. Hertzberg PPoPP 2006 Introductory TM Sales Pitch Two legs
More informationScheduling Transactions in Replicated Distributed Software Transactional Memory
Scheduling Transactions in Replicated Distributed Software Transactional Memory Junwhan Kim and Binoy Ravindran ECE Department, Virginia Tech, Blacksburg, VA, 2461 Email: junwhan, binoy@vt.edu Abstract
More informationLecture 7: Transactional Memory Intro. Topics: introduction to transactional memory, lazy implementation
Lecture 7: Transactional Memory Intro Topics: introduction to transactional memory, lazy implementation 1 Transactions New paradigm to simplify programming instead of lock-unlock, use transaction begin-end
More informationLinked Lists: The Role of Locking. Erez Petrank Technion
Linked Lists: The Role of Locking Erez Petrank Technion Why Data Structures? Concurrent Data Structures are building blocks Used as libraries Construction principles apply broadly This Lecture Designing
More informationReminder from last time
Concurrent systems Lecture 7: Crash recovery, lock-free programming, and transactional memory DrRobert N. M. Watson 1 Reminder from last time History graphs; good (and bad) schedules Isolation vs. strict
More informationByteSTM: Java Software Transactional Memory at the Virtual Machine Level
ByteSTM: Java Software Transactional Memory at the Virtual Machine Level Mohamed Mohamedin Thesis submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment
More informationAn Evaluation of Distributed Concurrency Control. Harding, Aken, Pavlo and Stonebraker Presented by: Thamir Qadah For CS590-BDS
An Evaluation of Distributed Concurrency Control Harding, Aken, Pavlo and Stonebraker Presented by: Thamir Qadah For CS590-BDS 1 Outline Motivation System Architecture Implemented Distributed CC protocols
More informationLecture 21: Transactional Memory. Topics: Hardware TM basics, different implementations
Lecture 21: Transactional Memory Topics: Hardware TM basics, different implementations 1 Transactions New paradigm to simplify programming instead of lock-unlock, use transaction begin-end locks are blocking,
More informationHardware Transactional Memory on Haswell
Hardware Transactional Memory on Haswell Viktor Leis Technische Universität München 1 / 15 Introduction transactional memory is a very elegant programming model transaction { transaction { a = a 10; c
More informationTransactional Memory. Yaohua Li and Siming Chen. Yaohua Li and Siming Chen Transactional Memory 1 / 41
Transactional Memory Yaohua Li and Siming Chen Yaohua Li and Siming Chen Transactional Memory 1 / 41 Background Processor hits physical limit on transistor density Cannot simply put more transistors to
More informationTowards a Software Transactional Memory for Graphics Processors
Eurographics Symposium on Parallel Graphics and Visualization (21) J. Ahrens, K. Debattista, and R. Pajarola (Editors) Towards a Software Transactional Memory for Graphics Processors Daniel Cederman, Philippas
More informationTransactional Memory. Prof. Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Tech
Transactional Memory Prof. Hsien-Hsin S. Lee School of Electrical and Computer Engineering Georgia Tech (Adapted from Stanford TCC group and MIT SuperTech Group) Motivation Uniprocessor Systems Frequency
More informationTransactional Memory. Concurrency unlocked Programming. Bingsheng Wang TM Operating Systems
Concurrency unlocked Programming Bingsheng Wang TM Operating Systems 1 Outline Background Motivation Database Transaction Transactional Memory History Transactional Memory Example Mechanisms Software Transactional
More informationTransac'onal Libraries Alexander Spiegelman *, Guy Golan-Gueta, and Idit Keidar * Technion Yahoo Research
Transac'onal Libraries Alexander Spiegelman *, Guy Golan-Gueta, and Idit Keidar * * Technion Yahoo Research 1 Mul'-Threading is Everywhere 2 Agenda Mo@va@on Concurrent Data Structure Libraries (CDSLs)
More informationOn Improving Distributed Transactional Memory
On Improving Distributed Transactional Memory Alexandru Turcu Dissertation submitted to the Faculty of the Virginia Polytechnic Institute and State University in partial fulfillment of the requirements
More informationEazyHTM: Eager-Lazy Hardware Transactional Memory
EazyHTM: Eager-Lazy Hardware Transactional Memory Saša Tomić, Cristian Perfumo, Chinmay Kulkarni, Adrià Armejach, Adrián Cristal, Osman Unsal, Tim Harris, Mateo Valero Barcelona Supercomputing Center,
More informationTransactional Memory. Companion slides for The Art of Multiprocessor Programming by Maurice Herlihy & Nir Shavit
Transactional Memory Companion slides for The by Maurice Herlihy & Nir Shavit Our Vision for the Future In this course, we covered. Best practices New and clever ideas And common-sense observations. 2
More informationSynchronization. CSCI 5103 Operating Systems. Semaphore Usage. Bounded-Buffer Problem With Semaphores. Monitors Other Approaches
Synchronization CSCI 5103 Operating Systems Monitors Other Approaches Instructor: Abhishek Chandra 2 3 Semaphore Usage wait(s) Critical section signal(s) Each process must call wait and signal in correct
More informationEnsuring dependability and improving performance of transactional systems deployed on multi-core architectures
Ensuring dependability and improving performance of transactional systems deployed on multi-core architectures Mohamed Mohamedin Preliminary Examination Proposal submitted to the Faculty of the Virginia
More informationNON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY. Tim Harris, 28 November 2014
NON-BLOCKING DATA STRUCTURES AND TRANSACTIONAL MEMORY Tim Harris, 28 November 2014 Lecture 8 Problems with locks Atomic blocks and composition Hardware transactional memory Software transactional memory
More informationTransactifying Apache s Cache Module
H. Eran O. Lutzky Z. Guz I. Keidar Department of Electrical Engineering Technion Israel Institute of Technology SYSTOR 2009 The Israeli Experimental Systems Conference Outline 1 Why legacy applications
More informationPortland State University ECE 588/688. Transactional Memory
Portland State University ECE 588/688 Transactional Memory Copyright by Alaa Alameldeen 2018 Issues with Lock Synchronization Priority Inversion A lower-priority thread is preempted while holding a lock
More informationRelaxing Concurrency Control in Transactional Memory. Utku Aydonat
Relaxing Concurrency Control in Transactional Memory by Utku Aydonat A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of The Edward S. Rogers
More informationThe Multicore Transformation
Ubiquity Symposium The Multicore Transformation The Future of Synchronization on Multicores by Maurice Herlihy Editor s Introduction Synchronization bugs such as data races and deadlocks make every programmer
More informationScalable Software Transactional Memory for Chapel High-Productivity Language
Scalable Software Transactional Memory for Chapel High-Productivity Language Srinivas Sridharan and Peter Kogge, U. Notre Dame Brad Chamberlain, Cray Inc Jeffrey Vetter, Future Technologies Group, ORNL
More informationMulti-Core Computing with Transactional Memory. Johannes Schneider and Prof. Roger Wattenhofer
Multi-Core Computing with Transactional Memory Johannes Schneider and Prof. Roger Wattenhofer 1 Overview Introduction Difficulties with parallel (multi-core) programming A (partial) solution: Transactional
More informationDependence-Aware Transactional Memory for Increased Concurrency. Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel University of Texas, Austin
Dependence-Aware Transactional Memory for Increased Concurrency Hany E. Ramadan, Christopher J. Rossbach, Emmett Witchel University of Texas, Austin Concurrency Conundrum Challenge: CMP ubiquity Parallel
More informationBuilding Efficient Concurrent Graph Object through Composition of List-based Set
Building Efficient Concurrent Graph Object through Composition of List-based Set Sathya Peri Muktikanta Sa Nandini Singhal Department of Computer Science & Engineering Indian Institute of Technology Hyderabad
More informationDisjoint- Access Parallelism: Impossibility, Possibility, and Cost of Transactional Memory Implementations
Disjoint- Access Parallelism: Impossibility, Possibility, and Cost of Transactional Memory Implementations Sebastiano Peluso, Roberto Palmieri, Paolo Romano 2, Binoy Ravindran and Francesco Quaglia 3 2
More informationProgramming with Transactional Memory
Programming with Transactional Memory Brian D. Carlstrom Computer Systems Laboratory Stanford University http://tcc.stanford.edu The Problem: The free lunch is over Chip manufacturers have switched from
More informationAccelerating Irregular Computations with Hardware Transactional Memory and Active Messages
MACIEJ BESTA, TORSTEN HOEFLER spcl.inf.ethz.ch Accelerating Irregular Computations with Hardware Transactional Memory and Active Messages LARGE-SCALE IRREGULAR GRAPH PROCESSING Becoming more important
More informationExtracting Parallelism from Legacy Sequential Code Using Software Transactional Memory
Extracting Parallelism from Legacy Sequential Code Using Software Transactional Memory Mohamed M. Saad Preliminary Examination Proposal submitted to the Faculty of the Virginia Polytechnic Institute and
More informationInvyswell: A HyTM for Haswell RTM. Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy
Invyswell: A HyTM for Haswell RTM Irina Calciu, Justin Gottschlich, Tatiana Shpeisman, Gilles Pokam, Maurice Herlihy Multicore Performance Scaling u Problem: Locking u Solution: HTM? u IBM BG/Q, zec12,
More informationDBT Tool. DBT Framework
Thread-Safe Dynamic Binary Translation using Transactional Memory JaeWoong Chung,, Michael Dalton, Hari Kannan, Christos Kozyrakis Computer Systems Laboratory Stanford University http://csl.stanford.edu
More informationAtomic Transac1ons. Atomic Transactions. Q1: What if network fails before deposit? Q2: What if sequence is interrupted by another sequence?
CPSC-4/6: Operang Systems Atomic Transactions The Transaction Model / Primitives Serializability Implementation Serialization Graphs 2-Phase Locking Optimistic Concurrency Control Transactional Memory
More informationConflict Detection and Validation Strategies for Software Transactional Memory
Conflict Detection and Validation Strategies for Software Transactional Memory Michael F. Spear, Virendra J. Marathe, William N. Scherer III, and Michael L. Scott University of Rochester www.cs.rochester.edu/research/synchronization/
More informationTradeoffs in Transactional Memory Virtualization
Tradeoffs in Transactional Memory Virtualization JaeWoong Chung Chi Cao Minh, Austen McDonald, Travis Skare, Hassan Chafi,, Brian D. Carlstrom, Christos Kozyrakis, Kunle Olukotun Computer Systems Lab Stanford
More informationSystem Challenges and Opportunities for Transactional Memory
System Challenges and Opportunities for Transactional Memory JaeWoong Chung Computer System Lab Stanford University My thesis is about Computer system design that help leveraging hardware parallelism Transactional
More informationMassimiliano Ghilardi
7 th European Lisp Symposium Massimiliano Ghilardi May 5-6, 2014 IRCAM, Paris, France High performance concurrency in Common Lisp hybrid transactional memory with STMX 2 Beautiful and fast concurrency
More informationbool Account::withdraw(int val) { atomic { if(balance > val) { balance = balance val; return true; } else return false; } }
Transac'onal Memory Acknowledgement: Slides in part adopted from: 1. a talk on Intel TSX from Intel Developer's Forum in 2012 2. the companion slides for the book "The Art of Mul'processor Programming"
More informationSpeculative Locks. Dept. of Computer Science
Speculative Locks José éf. Martínez and djosep Torrellas Dept. of Computer Science University it of Illinois i at Urbana-Champaign Motivation Lock granularity a trade-off: Fine grain greater concurrency
More informationABORTING CONFLICTING TRANSACTIONS IN AN STM
Committing ABORTING CONFLICTING TRANSACTIONS IN AN STM PPOPP 09 2/17/2009 Hany Ramadan, Indrajit Roy, Emmett Witchel University of Texas at Austin Maurice Herlihy Brown University TM AND ITS DISCONTENTS
More informationEnhancing efficiency of Hybrid Transactional Memory via Dynamic Data Partitioning Schemes
Enhancing efficiency of Hybrid Transactional Memory via Dynamic Data Partitioning Schemes Pedro Raminhas Instituto Superior Técnico, Universidade de Lisboa Lisbon, Portugal Email: pedro.raminhas@tecnico.ulisboa.pt
More informationOptimistic Preventive Replication in a Database Cluster
Optimistic Preventive Replication in a Database Cluster Cédric Coulon, Esther Pacitti, Patrick Valduriez INRIA and LINA, University of Nantes France {Cedric.Coulon, Esther.Pacitti}@lina.univ-nantes.fr,
More informationFall 2012 Parallel Computer Architecture Lecture 16: Speculation II. Prof. Onur Mutlu Carnegie Mellon University 10/12/2012
18-742 Fall 2012 Parallel Computer Architecture Lecture 16: Speculation II Prof. Onur Mutlu Carnegie Mellon University 10/12/2012 Past Due: Review Assignments Was Due: Tuesday, October 9, 11:59pm. Sohi
More informationEarly Results Using Hardware Transactional Memory for High-Performance Computing Applications
Early Results Using Hardware Transactional Memory for High-Performance Computing Applications Sverker Holmgren sverker.holmgren@it.uu.se Karl Ljungkvist kalj0193@student.uu.se Martin Karlsson martin.karlsson@it.uu.se
More informationHiperTM: High Performance, Fault-Tolerant Transactional Memory
HiperTM: High Performance, Fault-Tolerant Transactional Memory Sachin Hirve, Roberto Palmieri 1, Binoy Ravindran Virginia Tech, Blacksburg VA 2461, USA Abstract We present HiperTM, a high performance active
More informationCommit Phase in Timestamp-based STM
Commit Phase in Timestamp-based STM Rui Zhang Dept. of Computer Science Rice University Houston, TX 77005, USA ruizhang@rice.edu Zoran Budimlić Dept. of Computer Science Rice University Houston, TX 77005,
More informationCache-Aware Lock-Free Queues for Multiple Producers/Consumers and Weak Memory Consistency
Cache-Aware Lock-Free Queues for Multiple Producers/Consumers and Weak Memory Consistency Anders Gidenstam Håkan Sundell Philippas Tsigas School of business and informatics University of Borås Distributed
More informationTransactional Memory, linking Theory and Practice
Transactional Memory, linking Theory and Practice Srivatsan Ravi Vincent Gramoli Victor Luchangco TU Berlin EPFL Sun Labs, Oracle Deutsche-Telekom Labs University of Neuchâtel ravi@net.t-labs.tu-berlin.de
More informationManaging Resource Limitation of Best-Effort HTM
Managing Resource Limitation of Best-Effort HTM Mohamed Mohamedin, Roberto Palmieri, Ahmed Hassan, Binoy Ravindran Abstract The first release of hardware transactional memory (HTM) as commodity processor
More informationRemote Transaction Commit: Centralizing Software Transactional Memory Commits
IEEE TRANSACTIONS ON COMPUTERS 1 Remote Transaction Commit: Centralizing Software Transactional Memory Commits Ahmed Hassan, Roberto Palmieri, and Binoy Ravindran Abstract Software Transactional Memory
More informationExploiting Hardware Transactional Memory for Efficient In-Memory Transaction Processing. Hao Qian, Zhaoguo Wang, Haibing Guan, Binyu Zang, Haibo Chen
Exploiting Hardware Transactional Memory for Efficient In-Memory Transaction Processing Hao Qian, Zhaoguo Wang, Haibing Guan, Binyu Zang, Haibo Chen Shanghai Key Laboratory of Scalable Computing and Systems
More informationLecture 12 Transactional Memory
CSCI-UA.0480-010 Special Topics: Multicore Programming Lecture 12 Transactional Memory Christopher Mitchell, Ph.D. cmitchell@cs.nyu.edu http://z80.me Database Background Databases have successfully exploited
More informationOn Improving Distributed Transactional Memory Through Nesting and Data Partitioning
On Improving Distributed Transactional Memory Through Nesting and Data Partitioning Alexandru Turcu Preliminary Examination Proposal submitted to the Faculty of the Virginia Polytechnic Institute and State
More informationLecture: Consistency Models, TM. Topics: consistency models, TM intro (Section 5.6)
Lecture: Consistency Models, TM Topics: consistency models, TM intro (Section 5.6) 1 Coherence Vs. Consistency Recall that coherence guarantees (i) that a write will eventually be seen by other processors,
More informationImplementing Rollback: Copy. 2PL: Rollback. Implementing Rollback: Undo. 8L for Part IB Handout 4. Concurrent Systems. Dr.
Concurrent Systems 8L for Part IB Handout 4 Dr. Steven Hand Implementing Rollback: Undo One strategy is to undo operations, e.g. Keep a log of all operations, in order: O 1, O 2,.. O n On abort, undo changes
More informationLecture: Consistency Models, TM
Lecture: Consistency Models, TM Topics: consistency models, TM intro (Section 5.6) No class on Monday (please watch TM videos) Wednesday: TM wrap-up, interconnection networks 1 Coherence Vs. Consistency
More informationReal-Time Software Transactional Memory: Contention Managers, Time Bounds, and Implementations
Real-Time Software Transactional Memory: Contention Managers, Time Bounds, and Implementations Mohammed El-Shambakey Preliminary Examination Proposal submitted to the Faculty of the Virginia Polytechnic
More informationParallelizing SPECjbb2000 with Transactional Memory
Parallelizing SPECjbb2000 with Transactional Memory JaeWoong Chung, Chi Cao Minh, Brian D. Carlstrom, Christos Kozyrakis Computer Systems Laboratory Stanford University {jwchung, caominh, bdc, kozyraki}@stanford.edu
More informationarxiv: v1 [cs.db] 12 Nov 2018
The Impact of Timestamp Granularity in Optimistic Concurrency Control Yihe Huang Hao Bai Eddie Kohler Harvard University Barbara Liskov MIT Liuba Shrira Brandeis University arxiv:1811.04967v1 [cs.db] 12
More informationAgenda. Designing Transactional Memory Systems. Why not obstruction-free? Why lock-based?
Agenda Designing Transactional Memory Systems Part III: Lock-based STMs Pascal Felber University of Neuchatel Pascal.Felber@unine.ch Part I: Introduction Part II: Obstruction-free STMs Part III: Lock-based
More informationIncrementally Parallelizing. Twofold Speedup on a Quad-Core. Thread-Level Speculation. A Case Study with BerkeleyDB. What Am I Working on Now?
Incrementally Parallelizing Database Transactions with Thread-Level Speculation Todd C. Mowry Carnegie Mellon University (in collaboration with Chris Colohan, J. Gregory Steffan, and Anastasia Ailamaki)
More informationLecture: Transactional Memory. Topics: TM implementations
Lecture: Transactional Memory Topics: TM implementations 1 Summary of TM Benefits As easy to program as coarse-grain locks Performance similar to fine-grain locks Avoids deadlock 2 Design Space Data Versioning
More informationLow Overhead Concurrency Control for Partitioned Main Memory Databases
Low Overhead Concurrency Control for Partitioned Main Memory Databases Evan Jones, Daniel Abadi, Samuel Madden, June 2010, SIGMOD CS 848 May, 2016 Michael Abebe Background Motivations Database partitioning
More informationOutline. Database Tuning. Ideal Transaction. Concurrency Tuning Goals. Concurrency Tuning. Nikolaus Augsten. Lock Tuning. Unit 8 WS 2013/2014
Outline Database Tuning Nikolaus Augsten University of Salzburg Department of Computer Science Database Group 1 Unit 8 WS 2013/2014 Adapted from Database Tuning by Dennis Shasha and Philippe Bonnet. Nikolaus
More information