RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM. SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8)

Transcription

1 RIZALAFANDE CHE ISMAIL TKT. 3, BLOK A, PPK MIKRO-e KOMPLEKS PENGAJIAN KUKUM SYNTHESIS OF COMBINATIONAL LOGIC (Chapter 8)

2 HDL-BASED SYNTHESIS Modern ASIC design use HDL together with synthesis tool to create hardware realizations In theory, synthesis tools will automatically create an optimal gate-level realization In practice, results are dependent upon the skill of designers in writing RTL codes Synthesis tools supposed to produce a high-quality, optimal realization of the functionality described by a Verilog behavior Tools typically optimize for area and check for timing constraints Synthesis tools address three related problems: 1. Logic synthesis 2. RTL synthesis 3. Behavioral synthesis

3 HDL-BASED SYNTHESIS Design entry HDL behavioral model Functional simulation Timing simulation Design verification Physical optimization and implementation PLD FPGA, Arrays Standard cells HDL based design flow

4 HDL-BASED SYNTHESIS Logic synthesis Tools which operate on Boolean equations and produce optimal combinational logic and hence can be mapped into a physical realization example Boolean equation: y = a b + b c The general organization for logic synthesis tool:

5 HDL-BASED SYNTHESIS Behavioral description Technology libraries Translation engine Optimization engine Mapping engine Two-level logic functions Optimized multi-level logic functions Technology implementation

6 HDL-BASED SYNTHESIS RTL synthesis Transforms a behavior described in terms of operations on registers, signals and constraints into an optimal combinational logic and thus map the result into the target technology RTL description represents either a FSM or a more general machine (data-flow graphs)

7 HDL-BASED SYNTHESIS Behavioral synthesis Tools that synthesize datapath elements, control units and memory A relatively young technology, but successful tools have been developed supporting behavioral synthesis for DSP applications Poses the great challenge to EDA tools because there are many algorithms still cannot be synthesized easily

8 BENEFITS OF SYNTHESIS Synthesis methodology provide several benefits to all designers: Less time to write a Verilog code and synthesize into gate-level realization of a huge circuit rather than using gate-level entry The ease of writing, changing or substituting Verilog descriptions encourages architectural exploration The optimal circuit generated can be easily map into the target technology either FPGA or ASIC without having to re-optimize design Incorporate documentation within the design, thereby reducing the volume of documentation that must be kept in other archives

9 SYNTHESIS METHODOLOGY Focuses on the overall functionality of the design and creates a top-down architectural partition Timing constraints and area are used to synthesize a gate-level hardware realization to ensure that the timing and functionality of the design meet specifications The tools are not cheap and need designers to learn the technology and a new language

10 SYNTHESIS METHODOLOGY The synthesis methodology has some rules that apply to all synthesis tools: Avoid referencing the same variables in more than one cyclic (always) behavior can cause races in the software Advisable to use only synchronous re-settable flipflops in the design The synthesis tools can be influence by the designers in terms of clocking scheme, partition of the design hierarchy and instantiation of pre-defined modules

11 VENDOR SUPPORT Very hard to all vendors to support the entire language serves in several tools Strongly recommended to avoid any technologydependent descriptions For example, the propagation delay of a gate should not be included in the description Expressions which perform Boolean operation on the logic values x and z also need to be avoid

12 VENDOR SUPPORT Commonly supported Verilog constructs: Module declaration Port modes: input, output, inout Parameter declaration Connectivity nets: wire, tri, wand, wor, supply0, supply1 Register variables: reg, integer Integer types in binary, decimal, octal, hex formats Module and macromodule instantiation Continuous assignments Shift operator Conditional operator Concatenation operator PCA (assign deassign) Procedural block statements (begin end), case, default Branching: if, if else, if else if

13 VENDOR SUPPORT Unsupported and ignored constructs: Timing and event control Case equality, inequality Fork join Forever While Wait Initial Force release Cmos, rcmos, rnmos, nmos, pmos, rpmos Intra-assignment timing control Delay specifications Weak0, weak1, strong0, strong1, pull0, pull1

14 STYLES FOR SYNTHESIS OF COMBINATIONAL LOGIC Combinational synthesis from a netlist of primitives Combinational logic can be synthesized from a netlist of gate-level Verilog primitives module or (w1,x1,x2); or (w2,x3,x4); or (w3,x3,x4); nand (y,w1,w2,w3,en); X1 X2 X3 X4 en y endmodule

15 STYLES FOR SYNTHESIS OF COMBINATIONAL LOGIC Combinational synthesis from UDPs Synthesis tool can operate on a UDP to first obtain an equivalent representation in terms of Boolean expressions, and then optimize the logic module. table // inputs output // a b c y 0 1? : 1; 0 0? : 0; 1? 1 : 1; 1? 0 : 0; endtable C A B Y

16 STYLES FOR SYNTHESIS OF COMBINATIONAL LOGIC Combinational synthesis from continuous assignments Synthesis tool translates continuous assignment statement into a set of equivalent Boolean equations which can be optimized simultaneously module Assign y = ~(enable & (x1 x2) & (x3 x4)); endmodule X1 X2 X3 X4 en y

17 STYLES FOR SYNTHESIS OF COMBINATIONAL LOGIC Combinational synthesis from a cyclic behavior Combinational logic can also be described by a cyclic behavior but failure to assign value to the output under all events resulting in producing a design with unwanted latches after performing synthesis process module (enable or x1 or x2 or x3 or x4) begin assign y = ~(enable & (x1 x2) & (x3 x4)); end endmodule X1 X2 X3 X4 en y

18 STYLES FOR SYNTHESIS OF COMBINATIONAL LOGIC Combinational synthesis from a function or task Functions Task - Represent combinational logic because the value produced by a function depends only upon the values of its arguments - As a general rule, incomplete case statements and incomplete conditionals should be avoid in order to implement combinational logic - Implementing combinational logic similar with functions but restricted for not using timing control constructs in any procedural code