IMPLEMENTATION OF EFFICIENT AND HIGH SPEED AES ALGORITHM FOR SECURED DATA TRANSMISSION

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1 International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN X Vol.2, Issue 3 (Spl.) Sep TJPRC Pvt. Ltd., IMPLEMENTATION OF EFFICIENT AND HIGH SPEED AES ALGORITHM FOR SECURED DATA TRANSMISSION 1 D.V.N SUKANYA, 2 T.ASHOK KUMAR & 3 N.SURESH BABU Department of Electronics and Communication Engineering, Chirala Engineering College, Chirala, India ABSTRACT This paper presents novel high-speed architectures for the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSubBytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of sub pipelining can be further explored. The Advanced Encryption Algorithm (AES), a symmetric block cipher algorithm that can processes blocks of 128-b. The input and output for the AES algorithm each consist of sequence of 128-b (digit with values of 0 or 1). These sequences will sometimes refer to as blocks and the number of bits they contain will be referred to as their length. Internally, the AES algorithm s operation is are performed on a two-dimensional array of bytes. The state consists of four rows of bytes, each containing Nb bytes, where Nb is the block length. Here Nb = 4, which reflects the number of 32-b words (number of columns) in the state KEYWORDS: Cryptography, Encryption and Decryption Algorithms, Secret Key INTRODUCTION CRYPTOGRAPHY plays an important role in the security of data transmission. In January 1997, the National Institute of Standards and Technology (NIST) invited proposals for new algorithms for the Advanced Encryption Standard (AES) to replace the old Data Encryption Standard (DES). After two rounds of evaluation on the 15 candidate algorithms, NIST selected the Rijndael as the AES algorithm [1] in October The AES algorithm has broad applications, including smart cards and cellular phones, WWW servers and automated teller machines (ATMs), and digital video recorders. Compared to software implementations, hardware implementations of the AES algorithm provide more physical security as well as higher speed. Three architectural optimization approaches can be employed to speed up the hardware implementations: pipelining, subpipelining, and loop-unrolling. Among these approaches, the subpipelined architecture can achieve maximum speedup and optimum speed area ratio in non-feedback modes. In order to explore the advantage of subpipelining further, each round unit needs to be divided into more substages with equal delay. However, the SubBytes and the InvSubBytes in the AES algorithm are traditionally implemented by look-up tables (LUT) [2] [6]. In LUT-based approaches, it can be observed that the unbreakable delay of LUTs is longer than the total delay of the rest of the transformations in each round unit. This feature prohibits each round unit from being divided into more than two substages to achieve any further speedup. CONVENTIONAL CRYPTOSYSTEM A symmetric cryptosystem is shown in figure: 1 and has five ingredients: 1. Plain text: this is the original message or data that fed into the algorithm as input. 2. Encryption algorithm: the algorithm performs various substitutions and transformations on the plaintext.

2 23 Implementation of Efficient and High Speed AES Algorithm for Secured Data Transmission 3. Secret key: this is also an input to the algorithm and its value is independent of the plaintext. The algorithm will produce a different output depending on the specific key. 4. Cipher text: this is the scrambled message produced as output. It depends on the plaintext and the secret key. 5. Decryption algorithm: this is essentially the encryption algorithm run in reverse. It takes the ciphertext and the secret key and produces the original plaintext. METHODOLOGY The AES Algorithm is a symmetric-key cipher, in which both the sender and the receiver use a single key for encryption and decryption. The data block length is fixed to be 128 bits, while the length can be 128, 192, or 256 bits. In addition, the AES algorithm is an iterative algorithm. Each iteration can be called a round, and the total number of rounds is 10,12, or 14, when key length is 128,192, or 256, respectively. The 128 bit data block is divided into 16 bytes. These bytes are mapped to a 4x4 array called the State, and all the internal operations of the AES algorithm are performed on the State. The encryption process is iterative in nature. Each iterations are known as rounds. For each round 128 bit input data and 128 bit key is required. That is, need 4 words of key in one round. So the input key must be expanded to the required number of words, which depends upon the number of rounds. The output of each round serves as input of next stage. In AES system, same secret key is used for both encryption and decryption. So it provides simplicity in design. The input to the encryption algorithm is a single 128-bit block.this block is copied into the State array, which is a square matrix of bytes. State array is modified at each stage of encryption. In the encryption of the AES algorithm (Figure.2), each round except the final round consists of four transformations: 1. SubBytes: Operates in each byte of the State independently. Each byte is substituted by corresponding byte in the S-box.

3 D.V.N Sukanya, T.Ashok Kumar & N.Suresh Babu ShiftRow: Cyclically shifts the rows of the State over different offsets. 3. MixColumn: In this operation the column of the State are considered as polynomials over GF (2⁸) and are multiplied with a fixed polynomial. The MixColumn component doesnot operate in the last round of the algorithm. 4. AddRoundKey: Involves bit-wise XOR operation. The substitute byte transformation, called the byte sub, is a simple table lookup. The process is shown in the Figure.6. AES defines a 16X16 matrix of byte values, called an S-Box that contains a permutation of all possible b values which is shown in the Table.1. Each individual byte of the state is mapped into a new byte in the following way: The leftmost 4-b of the byte value is used as a row value and the rightmost 4-b are used as a column value. These row and column values serve as indexes into the S-Box to select a unique 8-b output value. For example, the hexadecimal value {95} references row 9, column 5 of the S-Box, which contains the value {ad}. Accordingly, the value {95} is mapped into the value {ad}. Table 1: S Box The process of byte substitution is same for the decryption process but it makes use of inverse S-Box as shown in the Table.2, which is applied to each byte of the state [2]. Table 2: AES Inverse S Box In this step, a normal left circular shift operation is done where in the first row is not altered and the next three rows are moved by 1, 2, 3 bytes respectively [4]. Conceptually, this is shown in the Figure.3. Whereas in decryption transformation, the rows are subjected to right circular shift wherein the first row is untouched and row 2, 3 and 4 are shifted by 1, 2 and 3 bytes respectively. This process is shown in the Figure.4.

4 25 Implementation of Efficient and High Speed AES Algorithm for Secured Data Transmission Fig. 3: AES Shift Row operation Fig. 4: AES Inverse Shift Row Operation The mix column transformation operates on the state column-by-column, treating each column as a four term polynomial. The column is considered as polynomial over GF (28) and multiplied with modulo x4+1 with a fixed polynomial a(x), given by: a(x) = {03}x3+{01}x2+{01}x+{02} Let s`(x) = a(x) x s(x): As a result of this multiplication, the four bytes in a column are replaced by the following: And the illustrates of Mix column transformation is shown in the Figure.5 for the encryption process. Fig. 5: AES Mix Column Operation While for the decryption process the Inv mix column is inverse of the mix column transformation, where in it is multiplied with fixed polynomial a -1 (x), given by a -1 (x) = {0b}x 3 +{0d}x 2 +{09}x+{0e}

5 D.V.N Sukanya, T.Ashok Kumar & N.Suresh Babu 26 Let s`(x) = a -1 (x) x s(x): As a result of this multiplication, the four bytes in a column are replaced by the following: Similarly, the 128 bit key is depicted as a square matrix of bytes. The ordering of bytes within a matrix is by column. Key expansion is an important for both encryption and decryption. Fig. 6: Key Expansion Algorithm The AES key expansion algorithm takes as input a 4-word (16 bytes) key and produces a linear array of 44 words (176 bytes).this is sufficient to provide a 4-word round key for the initial Add Round Key stage and each of the 10 rounds of the cipher. The above Shown pseudo code describes the expansion. The key is copied into the first 4 words of the expanded key.the reminder of the expanded key is filled in 4 words at a time. Each added word w[i] depends on the immediately preceding word, w[i-1] and the word four positions back, w[i- 4]. In three out of four cases, a simple XOR is used. For a word whose position in the w array is a multiple of 4, a more complex function g is used. 1. RotWord performs a one-byte circular left shift on a word.this means that an input word [b0,b1,b2,b3] is transformed into [b1,b2,b3,b0]. 2. SubWord performs a byte substitution on each byte of its input word,using the S-box. 3. The result of step 1 and step2 is XORed with a round constant Rcon[j].

6 27 Implementation of Efficient and High Speed AES Algorithm for Secured Data Transmission The round constant is a word in which the three rightmost bytes are always 0.Thus the effect of XOR of a word with Rcon is to only perform an XOR on the left byte of the word.the round constant is for each round and is defined as Rcon[j] = ( RC[j],0,0,0), with RC[1]=1; RC[j]=2*RC[j-1] and with multiplication over the field GF(2^8). The values of RC[j] in hexadecimal are: Table 3: Round Constant Values EXPERIMENTAL ANALYSIS Each round has 4 operations and it is iterative in nature. So the output of first round is fed to the second round as input data and perform the same operatons with another set of keys. This process continued until the last round reach.in the last round,there is no mixcolumn operation.the State array obtained after the last round is the required cipher text for transmission (Figure 7). Fig. 7: Encrypted Data The 128 bit input data is encoded into another set of 128 bit data using 128 bit secret key. Fig.8.& 9 shows Output waveform for Encryption and for decryption respectively. Fig. 8: Output waveform for Encryption

7 D.V.N Sukanya, T.Ashok Kumar & N.Suresh Babu 28 Fig. 9: Output Waveform for Decryption Fig. 10: RTL Schematics CONCLUSIONS In this paper, efficient subpipelined architectures of the AES algorithm are presented. In order to explore the advantage of subpipelining further, the SubBytes/ InvSubBytes is implemented by combinational logic to avoid the unbreakable delay of LUTs in the traditional designs. The RTL Schematic and Design summary is shown in fig 10 &11. Fig. 11: Design Summary of AES ACKNOWLEDGEMENTS The authors would like to thank the anonymous reviewers for their comments whichh were very helpful in improving the quality and presentation of this paper.

8 29 Implementation of Efficient and High Speed AES Algorithm for Secured Data Transmission REFERENCES 1. Abdelfatah A. Yahya and Ayman M. Abdalla A Shuffle Image-Encryption Algorithm Department of Computer Science, Al-Zaytoonah University of Jordan, Journal of Computer Science 4 (12): , Xinmiao Zhang, Student Member,IEEE, and Keshab K. Parthi, Fellow, IEEE High-Speed VLSI Architecture for AES Algorithm IEEE Transactions on VLSI, Vol.12, No.19, September Alireza Hodjat, Student Member, IEEE, and Ingrid Verbauwhede, Senior Member, IEEE Area- Throughput Trade-Offs for Fully Pipelined30 to 70 Gbits/s AES Processors IEEE Transactions on Computers, Vol.55, no.4, April Pawel Chodowiec and Kris Gaj Very compact FPGA implementation of the AES Algorithm,in Proc. Of Cryptographic hardware and embedded system workshop,pp , F.Rodriguez-Henriquez,N.A Saquib and A. Diaz- Perez 4.2 Gbits/sec Single Chip FPGA implementation of the AES Algorithm, ElectronicsLetters, Vol.39, No.15, pp , N. Sklavos and O. Koufopavlou, Member, IEEE Architectures and VLSI Implementations of the AESProposal Rijndael IEEE Transactions on Computers, Vol. 51, No. 12, December H. Kuo and I. Verbauwhede, Architectural optimization for a 1.82 Gbits/sec VLSI implementation of the AES Rijndael algorithm, in Proc. CHES 2001, pp , Paris, France, May M. McLoone and J. V. McCanny, Rijndael FPGA implementation utilizing look-up tables, in IEEEWorkshop on Signal Processing Systems, pp , Sept AUTHORS PROFILE D.V.N.Sukanya is pursuing M.Tech in VLSI &ES at Chirala Engineering College,Chirala. T.Ashok kumar,m.tech in CSE from Anna University Working as Assoc.prof in ECE Dept. CEC,Chirala. He has 5 years of teaching Experience. Prof.N.Suresh Babu is Vice- Principal & HOD of ECE Dept in CEC,Chirala.He got his M.Tech in Microwave Engineering from Birla Innstitute of technology, Ranchi. He has 13 years of teaching Experience and 2 Years of Industrial Experience in various organisations.