Layout Compliance for Triple Patterning Lithography: An Iterative Approach

Transcription

1 Layout Compliane for Triple Patterning Lithography: An Iterative Approah Bei Yu, Gilda Garreton, David Z. Pan ECE Dept. University of Texas at Austin, Austin, TX, USA Orale Las, Orale Corporation, Redwood Shores, CA, USA 09/16/ / 27

2 Outline Introdution New Challenges in Triple Patterning Lithography (TPL) Layout Compliane Algorithms Results and Conlusions 2 / 27

3 Outline Introdution New Challenges in Triple Patterning Lithography (TPL) Layout Compliane Algorithms Results and Conlusions 3 / 27

4 Lithography Status & Challenges 10 [Courtesy Intel] 1 um 0.1 X Advaned lithography to extend 193nm lithography Now and near future: doule/triple/quadruple patterning Long term future: other advaned lithography 4 / 27

5 From Doule Patterning to Triple Patterning Mask 1 ITRS roadmap 28nm Single Patterning 22nm Doule Patterning 14nm Triple Patterning 11nm Quadruple Patterning stith Mask 2 Layout deomposition Patterning friendly design Mask 1 Mask 2 Mask 3 5 / 27

6 Previous Works in TPL Layout Deomposition ILP or SAT [Cork+,SPIE 08][Yu+,ICCAD 11][Cork+,SPIE 13] Greedy or Heuristi [Ghaida+,SPIE 11][Fang+,DAC 12] [Kuang+,DAC 13][Yu+,DAC 14][Fang+,SPIE 14] SDP or Graph ased (trade-off) [Yu+, ICCAD 11][Chen+,ISQED 13][Yu+,ICCAD 13] Limitations: an NOT guarantee TPL friendly (a) () 6 / 27

7 Layout Compliane Prolem Formulation Input: Input layout patterns (may not e TPL friendly) Minimum oloring distane min s a a1 a1 d a2 d2 d1 a2 d2 d1 (a) () () Output: Apply layout deomposition and layout modifiation Remove all onflits 7 / 27

8 Layout Deomposition v.s. Layout Compliane a a a d d d (a) Input layout () Layout deomposition () Layout Modifiation Layout Compliane = Layout Deomposition + Layout Modifiation 8 / 27

9 Outline Introdution New Challenges in Triple Patterning Lithography (TPL) Layout Compliane Algorithms Results and Conlusions 9 / 27

10 Challenge 1: NO Shortut in TPL Complexity Optimizing onflit & stith simultaneously is NP-hard for DPL/TPL. Shortut in DPL: Step y step Eah step an e optimally solved Input Layout Step 1: Conflit Minimization Step 2: Stith Minimization (a) () () TPL: NO suh shortut, as onflit minimization is NP-hard Door losed? 10 / 27

11 Challenge 2: Where do the onflits ome from? DPL: Detet odd-yle Long pattern hains (a) () TPL: NP-hard to detet But mostly loal 4-lique (a) () () 11 / 27

12 Challenge 3: Deomposer Cluthing at Straws Conflit # Greedy or heuristi: Fast ut ad quality SDP or graph searh: Tradeoff, still not good in performane Performane target ILP: Good performane ut expensive CPU runtime Gap Our performane target 12 / 27

13 Outline Introdution New Challenges in Triple Patterning Lithography (TPL) Layout Compliane Algorithms Step 1: Initial Layout Deomposition Step 2: Layout Modifiation Step 3: Inremental Layout Deomposition Results and Conlusions 13 / 27

14 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition 2. Layout Modifiation 3. Inremental Layout Deomposition Output Masks 14 / 27

15 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition 2. Layout Modifiation 3. Inremental Layout Deomposition Output Masks a d 14 / 27

16 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition a1 2. Layout Modifiation 3. Inremental Layout Deomposition a2 d1 Output Masks d2 14 / 27

17 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition native struture ehind onflit a1 2. Layout Modifiation 3. Inremental Layout Deomposition a2 d1 Output Masks d2 14 / 27

18 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition a1 2. Layout Modifiation 3. Inremental Layout Deomposition a2 d1 Output Masks d2 14 / 27

19 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition olor re-assignment region a1 2. Layout Modifiation 3. Inremental Layout Deomposition a2 d1 Output Masks d2 14 / 27

20 Overall Flow Input Layout Deomposition Graph Constrution 1. Fast Initial Layout Deomposition 2. Layout Modifiation 3. Inremental Layout Deomposition Output Masks a d 14 / 27

21 Step 1: Initial Layout Deomposition Our method: linear olor assignment Linear runtime omplexity [Yu+,DAC 14] a1 native struture ehind onflit a1 May leave some onflits to Step 2 & 3 Muh faster than ILP or SDP a2 d1 a2 d1 d2 d2 Runtime omparisions: 15 / 27

22 Step 1: Fast Layout Deomposition (ont.) But, Any oloring order results in Loal Optimality Example: order a---d a a d (a) () d Half Pith a a d d () (d) Color-Friendly Rules: a- tend to e with the same olor 16 / 27

23 Step 1: Fast Layout Deomposition (ont.) Peer Seletion: Three orders would e proessed simultaneously Best solution would e seleted Still Linear runtime omplexity Degree-Coloring 3Round-Coloring Sequene-Coloring 17 / 27

24 Step 1: Fast Layout Deomposition (ont.) Peer Seletion: Whole prolem a set of omponents Different omponents have different dominant orders Overall etter results than any single order 18 / 27

25 Fast Layout Deomposition Result Example Row y row Resolved in 0.1 seond 19 / 27

26 Step 2: Layout Modifiation Initial layout deomposition output: native onflit is laeled: (a) () Layout modifiation to reak down eah four-lique: (a) () 20 / 27

27 Step 3: Inremental Layout Deomposition Input: One layout region & stith# ound Output: olor re-assignment in the region a1 olor re-assignment region a1 Method: ranh-and-ound Early return if satisfy stith# ound a2 d1 a2 d1 d2 d2 Runtiem & stith# ound trade-off: 21 / 27

28 Step 3: Inremental Layout Deomposition Example (a) () () (d) a Deomposed result after initial layout deomposition. All layout patterns to e re-assigned olors are laeled. The onstruted loal deomposition graph. d The result of inremental layout deomposition. 22 / 27

29 Outline Introdution New Challenges in Triple Patterning Lithography (TPL) Layout Compliane Algorithms Results and Conlusions 23 / 27

30 Interfaed with open soure tool Eletri 24 / 27

31 Layout Compliane Results 25 / 27

32 Conlusions First attempt for TPL layout ompliane Failiating the advanement of patterning tehnique Conflit # Greedy or heuristi: Fast ut ad quality SDP or graph searh: Tradeoff, still not good in performane Performane target ILP: Good performane ut expensive CPU runtime Future works Timing issue Smarter automatially layout modifiation 26 / 27

33 27 / 27 Thank You!