Implementing Video and Image Processing Designs Using FPGAs. Click to add subtitle
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1 Implementing Video and Image Processing Designs Using FPGAs Click to add subtitle
2 Agenda Key trends in video and image processing Video and Image Processing Suite Model-based design for video processing Tutorial 2006 Altera Corporation 2
3 Video and Imaging With FPGAs Broadcast Infrastructure HDTV Display Medical Imaging HDTV Videoconferencing Security DVR HD Security Camera Consumer/Auto Display Document Imaging Military Imaging 2006 Altera Corporation 3
4 Key Trends in Video and Imaging Higher resolutions 3,000 x 3,000 (and higher): medical imaging, military, machine vision 4,096 x 1,714: digital cinema 1,920 x 1,080: HDTV, broadcast 1,280 x 720: video surveillance, videoconferencing Advanced video compression H.264, JPEG2000, VC Altera Corporation 4
5 Current Solutions Do Not Deliver Video/ Imaging ASSPs Not optimized for target applications Risk of obsolescence DSP Cannot achieve high definition in single device ASIC High development cost Cannot keep up with fast-evolving applications 2006 Altera Corporation 5
6 Altera s FPGA Solution High performance in a single device Fast time-to-market Easy to upgrade Low development cost Obsolescence proof Lower unit costs at high volumes 2006 Altera Corporation 6
7 Video Benchmarks Cost Normalized to FPGA x7 2D Filter 720P 7x7 2D Median Filter 720P FPGA HardCopy II DSP Only H.264 BP Encoder 720P H.264 BP Encoder 1,024x Channel H.264 BP Encoder CIF 4-Channel H.264 BP Encoder D1 H.264 MP Encoder D1 H.264 MP Encoder 1080i JPEG2000 Encoder D Altera Corporation 7
8 Altera Video and Image Processing Solutions Overview DSP Algorithm Design Flow VHDL/Verilog MATLAB/ Simulink DSP Builder Synplicity C to Hardware Mentor Celoxica Intellectual Property (IP) System Integration Altera Baseline Processing Functions Third-Party Compression and Processing Functions Altera and Third-Party Video I/O and Interface IP SOPC Builder, VHDL/Verilog Video Reference Design Devices and Dev. Kits Cyclone II, Stratix II, HardCopy II 2006 Altera Corporation 8
9 IP Examples Video PCI Express Serial Rapid I/O EMIF Interface ASI SDI I/O and System ATA HDD (Nuvation) MPEG2 Transport 10/100/1000 Ethernet DDR/DDR2 Controller Video and Image Processing Suite Pre-/Post-Processing Scaler Deinterlacer 2D FIR Filter 2D Median Filter Color Space Converter Chroma Resampler Gamma Corrector Alpha Blender Highest Quality HDTV Upconversion (Let It Wave) AES/DES/Sha-1 Encryption (CAST) Compression H.264 MP, HP (ATEME) H.264 BP (4i2i, CAST, W&W) H.264 CABAC/CAVLC (ATEME) H.264 Loop Filter (ATEME) MPEG4 SP/ASP (CAST, Barco) JPEG (CAST, Barco) JPEG2000 (CAST, Barco, Broadmotion) 2006 Altera Corporation 9
10 HDTV Upconversion Let It Wave Breakthrough super-resolution Bandlet technology for HDTV upconversion Broadcasting equipment Upconverter implemented on cost-effective Altera FPGA Main features Standard definition (SD) to high definition (HD) up to 1080P 2-frame delay Color conversion Per pixel automatic film mode and cadence detection Aspect ratio conversion Additional features Cross conversion 720P to 1080I HD to SD down conversion Video enhancement Board reference design available 2006 Altera Corporation 10
11 Video and Image Processing Suite
12 Altera Video and Image Processing Suite Baseline set of IP with standard interfaces and protocols that allow users to easily add their own proprietary algorithms Optimized for Altera FPGAs Works with any design flow RTL, model-based design, C-based design 2006 Altera Corporation 12
13 Video and Image Processing Suite Core Deinterlacer Color space converter Scaler Gamma corrector Alpha blending mixer Chroma resampler 2D filter 2D median filter Line buffer compiler Function Converts interlaced video formats to progressive video format Converts image data between a variety of different color spaces Resizes and clips image frames Performs gamma correction on a color space Mixes and blends multiple image streams, including picture-inpicture (PIP) Changes the sampling rate of the chroma data for image frames Implements a 3x3, 5x5, or 7x7 finite impulse response (FIR) filter on an image data stream to smooth or sharpen images Implements a 3x3, 5x5, or 7x7 filter that removes noise in an image by replacing each pixel value with the median of neighboring pixel values Efficiently maps image line buffers to Altera on-chip memory 2006 Altera Corporation 13
14 2D Filtering 2D FIR filter and 2D median filter 3x3, 5x5 or 7x7 filter sizes Useful for noise reduction and smoothing filters Supports symmetric optimization 2006 Altera Corporation 14
15 Color Format Conversion Supplied as three separate cores Color space converter Chroma resampler Gamma corrector Supports RGB (computer and studio formats) YIQ/YUV (NTSC, PAL, SECAM) YCbCr (4:4:4, 4:2:2, 4:2:0) 2006 Altera Corporation 15
16 Image Blending and Picture-in-Picture Mixing Multi-layer mixing (2 to 8 layers) Per-pixel alpha blending Run-time control of picture-in-picture location 2006 Altera Corporation 16
17 Scaling D1/SDTV: 720 x 480 HDTV 1080p: 1920 x 1080 Supports standard-resolution conversions Nearest neighbor or bilinear filtering Clipping 2006 Altera Corporation 17
18 Deinterlacing Bob and Weave supported Bob 1 Field Weave 2 Fields Bob T T+1/2 Weave T T+1/ Altera Corporation 18
19 Line Buffer Compiler Provides line buffers, making efficient use of FPGA internal memories Optimized for typical SD and HD resolutions Any number of bits per color plane Choose line length, width, number of lines 2006 Altera Corporation 19
20 Model-Based Design for Video Processing
21 Design Flow Starting with Model-Based Design DSP Builder for data path Design Simulation Creation of an SOPC Builder component SOPC Builder for system integration External RAM controllers Sources and sinks Processor integration Nios II or external processor Compile in Quartus II software 2006 Altera Corporation 21
22 Configure Blocks with GUI IP Toolbench Launched from Quartus II software or directly in DSP Builder 2006 Altera Corporation 22
23 DSP Builder Video Library Alpha blending mixer Chroma resampler Color space converter Gamma corrector Deinterlacer 2D FIR filter 2D median filter Scaler 2006 Altera Corporation 23
24 SOPC Builder System Integration DSP Builder Data Path SOPC Builder System Add Sources Sinks Arbitrated DDR, SDR Control 2006 Altera Corporation 24
25 Example 1: Single Input Video Channel Composite video input VGA output Composite Video Input (NTSC) NTSC Interfaces Data Interface Control Interface Deinterlacing Chroma Resampling Color Space Conversion (YCbCr RGB) Gamma Correction Scaling 2D 5x5 FIR Filter (Sharpening) Nios II Processor Static Image Picture-in- Picture Mixing Triple Buffer VGA Controller Video Output (VGA) External Memory 2006 Altera Corporation 25
26 Example 2: Single Input Video Channel SDI video input/output SDI Video Source SDI Data Interface Avalon Control Interface Deinterlacing Chroma Resampling Color Space Conversion (YCbCr RGB) Scaling Triple Buffer SDI SDI Video External Memory 2006 Altera Corporation 26
27 Example 3: Multiple Video Channel Input Composite Video Input (NTSC) Dual composite video input VGA output Data Interface Avalon Control Interface NTSC Interface Deinterlacing Chroma Resampling Color Space Conversion (YCbCr RGB) Gamma Correction Scaling 2D 5x5 FIR Filter (Sharpening) Nios II Processor Picture-in- Picture Mixing Triple Buffer VGA Controller Video Output (VGA) Triple Buffer Composite Video Input (NTSC) External Memory Triple Buffer NTSC Interface Deinterlacing Chroma Resampling Color Space Conversion (YCbCr RGB) Gamma Correction Scaling 2D 5x5 FIR Filter (Sharpening) 2006 Altera Corporation 27
28 Video and Image Processing (VIP) Example Design
29 Example of a Video System System block diagram DSP Builder Implementation Simulation Conversion to HDL SOPC Builder integration Program hardware platform 2006 Altera Corporation 29
30 VIP Upconversion System NTSC Video Input: Composite Input on Video Daughtercard Video Upconversion Triple Buffer HD Video Output: VGA Controller DSP Builder DDR II SDRAM SOPC Builder 2006 Altera Corporation 30
31 Video Upconversion Data Path Entire data path is assembled in DSP Builder 640 x 480 Interlaced 60 Hz YCbCr 4:2:2 640 x 480 Progressive 30 Hz YCbCr 4:2:2 640 x 480 Progressive 30 Hz YCbCr 4:4:4 640 x 480 Progressive 30 Hz RGB 1,024 x 768 Progressive 30 Hz RGB 8 Deinterlacer MegaCore Chroma Resampler MegaCore Color Space Converter MegaCore Scaler MegaCore 8 Ready Valid Data Two Avalon Master Interfaces 2006 Altera Corporation 31
32 DSP Builder Implementation - Deinterlacer Parameterize Deinterlacer Up to 1920 x 1080 Supported Bob and Weave Supported 2006 Altera Corporation 32
33 DSP Builder Implementation: External Memory for Deinterlacer Parameterize External Memory (Simulation-Only Model) 2006 Altera Corporation 33
34 DSP Builder Implementation: Chroma Resampler 2006 Altera Corporation 34
35 DSP Builder Implementation: Color Space Converter 2006 Altera Corporation 35
36 DSP Builder Implementation: Scaler 2006 Altera Corporation 36
37 DSP Builder Implementation: Libraries Generated Deinterlacer Color Space Converter Chroma Resampler Scaler External Memory (Simulation) 2006 Altera Corporation 37
38 DSP Builder Implementation: Connecting Functions Connecting library functions is simple due to standard interface and protocol Connections Between the Color Space Converter and Scaler 2006 Altera Corporation 38
39 Simulation: Video Input Altera Corporation 39
40 Simulation: Generate Video Binary File Command Line Utility converts AVI file to a binary file for use within DSP Builder environment Also converts binary output to an AVI file for convenient playback 2006 Altera Corporation 40
41 Simulation: Video Output Altera Corporation 41
42 Simulation: Upconversion Subsystem 2006 Altera Corporation 42
43 Convert to VHDL: Signal Compiler 2006 Altera Corporation 43
44 Top-Level Design File in Quartus II 2006 Altera Corporation 44
45 System Integration: SOPC Builder NTSC BT.656 DSP Builder - Data Path Buffer VGA Out DDR Altera Corporation 45
46 Custom Hardware Generated custom video interfaces IP Available within reference design package 2006 Altera Corporation 46
47 NTSC Video Input Video data capture with TI TVP5146 decoder I2C is control interface for device configuration Controller designed in HDL Imported into SOPC Builder Y/C Syncs I2C Controller Video Data Capture Example Design Controller Daughter Card Clock (-25 MHz) SOPC System Clock (130 MHz) Dual-Clock FIFO NTSC Composite Input 8 Ready Valid Data 2006 Altera Corporation 47
48 Triple Buffer and VGA Output Allows inputs and output to run asynchronously and at different frame rates Video output: 1,024 x 768 progressive at 30 frame/s VGA output: must run at least 60 fps HDL design, imported into SOPC Builder Ready Valid Data Memory Memory Writer Reader 24 SOPC Builder Arbitration Logic Ready Valid Data Ready Valid Data 24 SOPC System VGA Clock Clock (130 MHz) (65 MHz) Dual-Clock VGA Syncs FIFO Generator R G B Sync DDR 2006 Altera Corporation 48
49 Video Development Kit, Cyclone II Edition Device: EP2C70 Bundled software: Quartus II development kit edition DSP Builder MATLAB/Simulink evaluation software Altera OpenCore Plus evaluation IP Includes video input daughter card 2006 Altera Corporation 49
50 Video Input Daughter Card Features: Dual composite video inputs (NTSC & PAL) Compatible with other Altera development boards that feature a Santa Cruz connector 2006 Altera Corporation 50
51 Download to Hardware Resource utilization 9,500 logic elements, 48 M4K, 11 multipliers Fits in EP2C15 device Program Video Development Kit, Cyclone II Edition Hardware debug JTAG/SignalTap logic analyzer 2006 Altera Corporation 51
52 Getting Started
53 Altera Video Solutions DSP Builder SOPC Builder Video IP Suite $995 Video Dev. Kits Daughter Card $195 Cyclone II $1,095 Stratix II GX $4,995 Video Processing Design Software Support Tools Intellectual Property (IP) Development Kits Reference Designs Partner IP and Design Services Altera Training 2006 Altera Corporation 53
54 Audio Video Development Kit, Stratix II GX Edition Device: EP2SGX90 Video interfaces: 4 SDI/HD-SDI channels DVI Audio interfaces: AES3/EBU, SPDIF High-speed data interfaces: ASI FireWire (IEEE1394) USB /100/1000 Ethernet Bundled with SDI and video processing reference design 2006 Altera Corporation 54
55 Get Started Now Product Description Ordering Code Price Video and Image Processing Suite 9 video and image processing IP cores IPS-VIDEO $995 Video Development Kit, Cyclone II Edition Cyclone II DSP board + video input daughtercard DK-VIDEO- 2C70N $1,095 Video Input Daughter Card 2 composite video inputs (NTSC/PAL Support) DC-VIDEO- TVP5146N $195 Audio Video Development Kit, Stratix II GX Edition Stratix II GX video board with ASI, SDI, DVI, Gigabit Ethernet, FireWire, USB2.0, S/PDIF, AES DK-VIDEO- 2SGX90N $4, Altera Corporation 55
56 Thank You Q & A
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