VHDL. Douglas L. Perry. Third Edition

Transcription

1 VHDL Douglas L. Perry Third Edition McGraw-Hill New York San Francisco Washington, D.C. Auckland Bogota Caracas Lisbon London Madrid Mexico City Milan Montreal New Delhi San Juan Singapore Sydney Tokyo Toronto if

2 CONTENTS Preface xv Chapter 1 Introduction to VHDL VHSIC Program VHDL as a Standard Learning VHDL VHDL Terms Traditional Design Methods Traditional Schematics Symbols Versus Entities Schematics Versus Architectures Component Instantiation Behavioral Descriptions Concurrent Signal Assignment Event Scheduling Statement Concurrency Sequential Behavior Process Statements Process Declarative Region Process Statement Part Process Execution Sequential Statements Architecture Selection Configuration Statements Power of Configurations Chapter 2 Behavioral Modeling Introduction to Behavioral Modeling Transport Versus Inertial Delay Inertial Delay Transport Delay Inertial Delay Model Transport Delay Model Simulation Deltas D ri vers Driver Creation Bad Multiple Driver Model

3 Generics 31 Block Statements 33 Guarded Blocks 37 Chapter 3 Sequential Processing 41 Process Statement 42 Sensitivity List 42 Process Example 42 Signal Assignment Versus variable Assignment 44 Incorrect Mux Example 45 Correct Mux Example 47 Sequential Statements 48 IF Statements 49 CASE Statements 50 LOOP Statements 52 NEXT Statement 55 EXIT Statement 56 ASSERT Statement 58 Assertion BNF 59 WAIT Statements 61 WAIT ON Signal 64 WAIT UNTIL Expression 64 WAIT FOR time_expression 64 Multiple WAIT Conditions 65 WAIT Time-Out 66 Sensitivity List Versus WAIT Statement 68 Concurrent Assignment Problem 69 Passive Processes 72 Chapter 4 Data Types 75 Object Types 76 Signal 76 Variables 78 Constants 79 Data Types 80 Scalar Types 81 Composite Types 88 Incomplete Types 100 File Types 104 File Type Caveats 107 Subtypes 107

4 IX Chapter 5 Subprograms and Packages Subprograms Function Conversion Functions Resolution Functions Procedures Packages Package Declaration Deferred Constants Subprogram Declaration Package Body Chapter 6 Predefined Attributes Value Kind Attributes Value Type Attributes Value Array Attributes Value Block Attributes Function Kind Attributes Function Type Attributes Function Array Attributes Function Signal Attributes Attributes EVENT and LAST_VALUE Attribute LAST_EVENT Attribute ACTIVE and LAST_ACTIVE Signal Kind Attributes Attribute DELAYED Attribute STABLE Attribute QUIET Attribute TRANSACTION Type Kind Attributes Range Kind Attributes Chapter 7 Configurations Default Configurations Component Configurations Lower-Level Configurations Entity-Architecture Pair Configuration Port Maps Mapping Library Entities Generics in Configurations

5 Generic Value Specification in Architecture Generic Specifications in Configurations Board-Socket-Chip Analogy Block Configurations Architecture Configurations Chapter 8 Chapter 9 Advanced Topics Overloading Subprogram Overloading Overloading Operators Aliases Qualified Expressions User-Defined Attributes Generate Statements Irregulär Generate Statement TextIO Synthesis Register Transfer Level Description Constraints Timing Constraints Clock Constraints Attributes Load Drive Arrival Time Technology Libraries Synthesis Translation Boolean Optimization Flattening Factoring Mapping to Gates Chapter 10 VHDL Synthesis Simple Gate Concurrent Assignment IF Control Flow Statements Case Control Flow Statements Simple Sequential Statements Asynchronous Reset

6 XI Asynchronous Preset and Clear More Complex Sequentia! Statements Four-Bit Shifter State Machine Example Chapter 11 High Level Design Flow RTL Simulation VHDL Synthesis Functional Gate Level Verification Place and Route Post Layout Urning Simulation Static Urning Chapter 12 Top-Level System Design CPU Design Top-Level System Operation Instructions Sample Instruction Representation CPU Top-Level Design Block Copy Operation Chapter 13 CPU: Synthesis Description ALU Comp Control Reg Regarray Shift Trireg Chapter 14 CPU: RTL Simulation Testbenches Kinds of Testbenches Stimulus Only Füll Testbench Simulator Specific Hybrid Testbenches Fast Testbench CPU Simulation

7 Chapter 15 CPU Design: Synthesis Results 365 Control Alu Comp Reg Regarray Shirt Tri reg Chapter 16 Place and Route Place and Route Process Placing and Routing the Device Setting up a project Reading in the Netlist and Performing Place and Route Analyzing the Results Chapter 1 7 CPU: VITAL Simulation VITAL Library VITAL Simulation Process Overview VITAL Implementation Simple VITAL Model VITAL Architecture Wire Delay Section Flip-Flop Example SDF File VITAL Simulation Back-Annotated Simulation Appendix A Standard Logic Package 415 Appendix B VHDL Reference Tables 437 Appendix C Reading VHDL BNF 447 Appendix D VHDL93 Updates Alias Attribute Changes Bit String Literal

8 DELAY_LENGTH Subtype Direct Instantiation Extended Identifiers File Operations Foreign Interface Generate Statement Changes Globally Static Assignment Groups Incremental Binding Postponed Process Pure and Impure Functions Pulse Reject Report Statement Shared Variables Shift Operators SLL shift left logical SRL shift right logical SLA shift left arithmetic SRA shift right arithmetic ROL rotate left ROR rotate right Syntax Consistency Unaffected XNOR Operator