CSC501 Operating Systems Principles. OS Structure

Transcription

1 CSC501 Operating Systems Principles OS Structure 1

2 Announcements q TA s office hour has changed Q Thursday 1:30pm 3:00pm, MRC-409C Q Or awang@ncsu.edu q From department: No audit allowed 2

3 Last Lecture q Introduction to OS Q Abstraction Q Separation of mechanisms and policies q Today: Q Computer architecture Q OS structure 3

4 Basic Computer Architecture q A (partial) list of hardware: Q Central processing unit (CPU) Q Memory management unit (MMU) Q Persistent storage (e.g., Disk) Q Peripheral devices (e.g., NIC) 4

5 Basic Computer Architecture the single core

6 Basic Computer Architecture q A (partial) list of hardware: Q Central processing unit (CPU) Q Memory management unit (MMU) Q Persistent storage (e.g., Disk) Q Peripheral devices (e.g., NIC) q Recent development Q Performance: Multiprocessor, Multicore Q Security: TPM 6

7 Multicore Architecture q Replicate multiple processor cores on a single die Core 1 Core 2 Core 3 Core 4 7

8 Why Multicore? qperformance Q Difficult to make single-core clock frequencies even higher Q Parallelism: Many new applications are multithreaded 8

9 The Memory Hierarchy q How many layers Q CPU Registers -> CPU Cache (L1, L2, L3) -> Memory -> Disk q Why? Q Motivated by the mismatch between processor and memory speed Q Motivated by the fact that most programs have a high degree of locality in their accesses v v Spatial locality: accessing things nearby recent accesses Temporary locality: reusing an item previously accessed 9

10 The Memory Hierarchy q Comparison between different types of memory Q Metric: Size, Speed, Cost Register Cache Memory HDD size: speed: $/Mbyte: B 2 ns 32KB - 4MB 4 ns $100/MB 512 MB 60 ns $1.50/MB 20 GB 8 ms $0.05/MB larger, slower, cheaper 10

11 The Memory Hierarchy -- Multicore q Single-core chip: Q L1, L2, q Multi-core chips: Q L1 s private? Q L2 s private? Q Memory private? C O R E 1 L1 C O R E 0 L2 L1 memory L1 is private Example: Dual-core Intel Xeon processors 2 11

12 The Memory Hierarchy -- Multicore C O R E 1 L1 C O R E 0 L1 C O R E 1 L1 C O R E 0 L1 L2 L2 L2 L2 L3 L3 memory Both L1 and L2 are private Examples: AMD Opteron, AMD Athlon, Intel Pentium D memory A design with L3 s Example: Intel Itanium 2 12

13 Private vs shared s q Advantages/disadvantages? 13

14 Private vs shared s q Advantages of private: Q They are closer to core, so faster access Q Reduces contention q Advantages of shared: Q Threads on different cores can share the same data Q More space available 14

15 C O R E 1 L1 L2 C O R E 0 L1 L2 Question: In multicore environment with private L1/L2, is there any serious issue we should address? memory 15

16 The coherence problem q Since we have private s, how to keep the data consistent across cores? Q Each core should perceive the memory as a monolithic array, shared by all the cores

17 Suppose variable x initially contains Core 1 Core 2 Core 3 Core 4 multi-core chip Main memory x=

18 Core 1 reads x Core 1 Core 2 Core 3 Core 4 x=15213 multi-core chip Main memory x=15213

19 Core 2 reads x Core 1 Core 2 Core 3 Core 4 x=15213 x=15213 multi-core chip Main memory x=15213

20 Core 1 writes to x, setting it to Core 1 Core 2 Core 3 Core 4 x=21660 x=15213 multi-core chip Main memory x=21660 assuming write-through s

21 Core 2 attempts to read x gets a stale copy Core 1 Core 2 Core 3 Core 4 Any solutions? x=21660 x=15213 multi-core chip Main memory x=21660

22 Solutions for coherence q This is a general problem with multiprocessors, not limited just to multi-core q There exist many solution algorithms, coherence protocols, etc. q A simple solution Q Invalidation-based protocol with snooping 22

23 Invalidation protocol with snooping q Invalidation: If a core writes to a data item, all other copies of this data item in other s are invalidated q Snooping: All cores continuously snoop (monitor) the bus connecting the cores. 23

24 Outline q Computer architecture q OS structure Q Monolithic Q Layered Q Microkernel 24

25 Monolithic user applications user/kernel boundary OS: procs+data hardware

26 Layer user filesystem inter-machine net. memory mgr (high) device mgr + drivers real-time clock mgr IPC process coord process mgr memory mgr (low) user/kernel boundary Why? hardware

27 Microkernel FS mem svr proc svr kernel user app user app user app user/kernel boundary? hardware

28 Comparison Monolithic Performance Extensibility Reliability Scalability Layered Microkernel Best In between Worst 28

29 Virtual Machines (VMs) q Old concept which is heavily revived today Q the real hardware is "cloned" in several identical VMs Q OS functionality built on top of the VM Guest OS Guest OS Guest OS Guest OS VMM Console OS Scheduler Memory Mgmt SCSI Driver Ethernet Driver CPU Memory disk nic nicnic

30 Lab 0 q Lab 0 is available on the web Q Due 1/20 at 11:45pm sharp Q Electronic submission (late assignments automatically rejected) 30

31 Next Lecture q Processes, threads, and synchronization q We will start class on time, so please don t come late! 31