Quine-McCluskey Algorithm

Size: px
Start display at page:

Download "Quine-McCluskey Algorithm"

Transcription

1 Quine-McCluskey Algorithm Useful for minimizing equations with more than 4 inputs. Like K-map, also uses combining theorem Allows for automation Chapter <>

2 Edward McCluskey (99-06) Pioneer in Electrical Engineering First president of IEEE Professor at Princeton, then Stanford 955: Quine-McCluskey Algorithm Chapter <>

3 Quine-McCluskey Algorithm Method:. s Table: List each minterm, sorted by the number of s it contains. Combine minterms.. Prime Implicant Table: When you can t combine anymore, list prime implicants and the minterms they cover. 3. Select Prime to cover all minterms. Chapter <3>

4 Quine-McCluskey Example ABC Y Chapter <4>

5 s Table Quine-McCluskey Example ABC Y of 's 0 Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Order the minterms by the number of s they have. Chapter <5>

6 s Table Quine-McCluskey Example ABC Y of 's 0 Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5) 0- m(,3) -0 m(,6) Combine minterms in adjacent groups (starting with the top group). To combine terms, minterm can differ (be or 0) in only place - indicates don t care Chapter <6>

7 s Table Quine-McCluskey Example ABC Y of 's 0 Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5) 0- m(,3) -0 m(,6) Size m(0,,,3) Combine minterms in adjacent groups (starting with the top group). To combine terms, minterm can differ (be or 0) in only place - (don t care) acts like another variable (0,, -) Match up - first. Chapter <7>

8 s Table Quine-McCluskey Example ABC Y of 's 0 Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5)* 0- m(,3) -0 m(,6)* Size m(0,,,3)* List prime implicants: Largest implicants containing a given minterm For example m(0,) is an implicant but not a prime implicant, because m(0,,,3) is a larger implicant containing those minterms. However, m(,5) is a prime implicant no larger implicant exists that contains minterm 5. Chapter <8>

9 Prime Implicant Table s Table Quine-McCluskey Example ABC Y of 's 0 Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5)* 0- m(,3) -0 m(,6)* Size m(0,,,3)* List prime implicants. Prime m(0,,,3) m(,5) m(,6) Minterms ABC Show which of the required minterms each includes. Chapter <9>

10 Prime Implicant Table s Table Quine-McCluskey Example ABC Y of 's 0 Prime m(0,,,3) m(,5) m(,6) Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Minterms Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5)* 0- m(,3) -0 m(,6)* Size m(0,,,3)* ABC Select columns with only. Corresponding prime implicants must be included in equation. Chapter <0>

11 Prime Implicant Table s Table Quine-McCluskey Example ABC Y of 's 0 Prime m(0,,,3) m(,5) m(,6) Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Minterms Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5)* 0- m(,3) -0 m(,6)* Size m(0,,,3)* ABC Select columns with only. Corresponding prime implicants must be included in equation. Chapter <>

12 Prime Implicant Table s Table Quine-McCluskey Example ABC Y of 's 0 Prime m(0,,,3) m(,5) m(,6) Size 000 m0 00 m 00 m 0 m3 0 m5 0 m6 Minterms Size 00- m(0,) 0-0 m(0,) 0- m(,3) -0 m(,5)* 0- m(,3) -0 m(,6)* Y = A + BC + BC ABC Chapter <> Size m(0,,,3)* Select columns with only. Corresponding prime implicants must be included in equation.

13 Quine-McCluskey Example ABCD Y Chapter <3>

14 s Table Quine-McCluskey Example ABCD Y of 's 3 Size 000 m 000 m 000 m4 000 m8 00 m3 00 m6 00 m9 00 m0 0 m4 Chapter <4>

15 s Table Quine-McCluskey Example ABCD Y of 's 3 Size 000 m 000 m 000 m4 000 m8 00 m3 00 m6 00 m9 00 m0 0 m4 Size 00- m(,3) -00 m(,9) 00- m(,3) 0-0 m(,6) -00 m(,0) 0-0 m(4,6) 00- m(8,9) 0-0 m(8,0) -0 m(6,4) -0 m(0,4) Chapter <5>

16 s Table Quine-McCluskey Example ABCD Y of 's 3 Size 000 m 000 m 000 m4 000 m8 00 m3 00 m6 00 m9 00 m0 0 m4 Size 00- m(,3) -00 m(,9) 00- m(,3) 0-0 m(,6) -00 m(,0) 0-0 m(4,6) 00- m(8,9) 0-0 m(8,0) -0 m(6,4) -0 m(0,4) Size m(,6,0,4) Chapter <6>

17 s Table Quine-McCluskey Example ABCD Y of 's 3 Size 000 m 000 m 000 m4 000 m8 00 m3 00 m6 00 m9 00 m0 0 m4 Size 00- m(,3)* -00 m(,9)* 00- m(,3)* 0-0 m(,6) -00 m(,0) 0-0 m(4,6)* 00- m(8,9)* 0-0 m(8,0)* -0 m(6,4) -0 m(0,4) Size m(,6,0,4)* Chapter <7>

18 Prime Implicant Table s Table Quine-McCluskey Example ABCD Y of 's 3 Size 000 m 000 m 000 m4 000 m8 00 m3 00 m6 00 m9 00 m0 0 m4 Prime m(,6,0,4) m(,3) m(,9) m(,3) m(4,6) m(8,9) m(8,0) Size 00- m(,3)* -00 m(,9)* 00- m(,3)* 0-0 m(,6) -00 m(,0) 0-0 m(4,6)* 00- m(8,9)* 0-0 m(8,0)* -0 m(6,4) -0 m(0,4) Minterms Chapter <8> Size m(,6,0,4)* ABCD

19 Prime Implicant Table Quine-McCluskey Example ABCD Y Prime m(,6,0,4) m(,3) m(,9) m(,3) m(4,6) m(8,9) m(8,0) Minterms ABCD Chapter <9>

20 Prime Implicant Table Quine-McCluskey Example ABCD Y Prime m(,6,0,4) m(,3) m(,9) m(,3) m(4,6) m(8,9) m(8,0) Minterms ABCD Chapter <0>

21 Prime Implicant Table Quine-McCluskey Example ABCD Y Prime m(,6,0,4) m(,3) m(,9) m(,3) m(4,6) m(8,9) m(8,0) Minterms ABCD Chapter <>

22 Prime Implicant Table Quine-McCluskey Example ABCD Y Prime m(,6,0,4) m(,3) m(,9) m(,3) m(4,6) m(8,9) m(8,0) Minterms ABCD Chapter <>

23 Prime Implicant Table Quine-McCluskey Example ABCD Y Prime m(,6,0,4) m(,3) m(,9) m(,3) m(4,6) m(8,9) m(8,0) Minterms ABCD Y = CD + ABD + ABC Chapter <3>

Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1

Synthesis 1. 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, Typeset by FoilTEX 1 Synthesis 1 1 Figures in this chapter taken from S. H. Gerez, Algorithms for VLSI Design Automation, Wiley, 1998. Typeset by FoilTEX 1 Introduction Logic synthesis is automatic generation of circuitry

More information

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map

Karnaugh Map (K-Map) Karnaugh Map. Karnaugh Map Examples. Ch. 2.4 Ch. 2.5 Simplification using K-map Karnaugh Map (K-Map) Ch. 2.4 Ch. 2.5 Simplification using K-map A graphical map method to simplify Boolean function up to 6 variables A diagram made up of squares Each square represents one minterm (or

More information

Larger K-maps. So far we have only discussed 2 and 3-variable K-maps. We can now create a 4-variable map in the

Larger K-maps. So far we have only discussed 2 and 3-variable K-maps. We can now create a 4-variable map in the EET 3 Chapter 3 7/3/2 PAGE - 23 Larger K-maps The -variable K-map So ar we have only discussed 2 and 3-variable K-maps. We can now create a -variable map in the same way that we created the 3-variable

More information

Introduction. The Quine-McCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick

Introduction. The Quine-McCluskey Method Handout 5 January 24, CSEE E6861y Prof. Steven Nowick CSEE E6861y Prof. Steven Nowick The Quine-McCluskey Method Handout 5 January 24, 2013 Introduction The Quine-McCluskey method is an exact algorithm which finds a minimum-cost sum-of-products implementation

More information

Combinational Logic Circuits Part III -Theoretical Foundations

Combinational Logic Circuits Part III -Theoretical Foundations Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic

More information

User s Manual. Ronwaldo A. Collado Diosdado Y. Tejoso Jr. CMSC 130 Logistic Design and Digital Computer Circuits Second Semester, A. Y.

User s Manual. Ronwaldo A. Collado Diosdado Y. Tejoso Jr. CMSC 130 Logistic Design and Digital Computer Circuits Second Semester, A. Y. The Quine-McCluskey Method, also known as the Tabulation Method is a specific step-by-step method that is ensured to generate a simplified standard-form expression for a function. Ronwaldo A. Collado Diosdado

More information

Switching Circuits & Logic Design

Switching Circuits & Logic Design Switching Circuits & Logic Design Jie-Hong Roland Jiang 江介宏 Department of Electrical Engineering National Taiwan University Fall 23 5 Karnaugh Maps K-map Walks and Gray Codes http://asicdigitaldesign.wordpress.com/28/9/26/k-maps-walks-and-gray-codes/

More information

3.4 QUINE MCCLUSKEY METHOD 73. f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD.

3.4 QUINE MCCLUSKEY METHOD 73. f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD. 3.4 QUINE MCCLUSKEY METHOD 73 FIGURE 3.22 f(a, B, C, D, E)¼B CD þ BCD. FIGURE 3.23 f(a, B, C, D, E)¼AC ĒþB CD þ BCDþĀBD. A¼1map are, 1, and 1, respectively, whereas the corresponding entries in the A¼0

More information

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey

CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input

More information

Introduction to Microprocessors and Digital Logic (ME262) Boolean Algebra and Logic Equations. Spring 2011

Introduction to Microprocessors and Digital Logic (ME262) Boolean Algebra and Logic Equations. Spring 2011 Introduction to Microprocessors and Digital (ME262) lgebra and Spring 2 Outline. lgebra 2. 3. Karnaugh Maps () 4. Two-variable 5. 6. 7. 2 lgebra s of Simplifying equations are defined in terms of inary

More information

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU. CH5 Karnaugh Maps. Lecturer: 吳安宇教授 Date:2006/10/20 ACCESS IC LAB CH5 Karnaugh Maps Lecturer: 吳安宇教授 Date:2006/0/20 CCESS IC L Problems in lgebraic Simplification The procedures are difficult to apply in a systematic way. It is difficult to tell when you have arrived

More information

A B AB CD Objectives:

A B AB CD Objectives: Objectives:. Four variables maps. 2. Simplification using prime implicants. 3. "on t care" conditions. 4. Summary.. Four variables Karnaugh maps Minterms A A m m m3 m2 A B C m4 C A B C m2 m8 C C m5 C m3

More information

Chapter 3 Simplification of Boolean functions

Chapter 3 Simplification of Boolean functions 3.1 Introduction Chapter 3 Simplification of Boolean functions In this chapter, we are going to discuss several methods for simplifying the Boolean function. What is the need for simplifying the Boolean

More information

CMPE223/CMSE222 Digital Logic

CMPE223/CMSE222 Digital Logic CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each

More information

SEE1223: Digital Electronics

SEE1223: Digital Electronics SEE223: Digital Electronics 3 Combinational Logic Design Zulkifil Md Yusof Dept. of Microelectronics and Computer Engineering The aculty of Electrical Engineering Universiti Teknologi Malaysia Karnaugh

More information

DKT 122/3 DIGITAL SYSTEM 1

DKT 122/3 DIGITAL SYSTEM 1 Company LOGO DKT 122/3 DIGITAL SYSTEM 1 BOOLEAN ALGEBRA (PART 2) Boolean Algebra Contents Boolean Operations & Expression Laws & Rules of Boolean algebra DeMorgan s Theorems Boolean analysis of logic circuits

More information

ECE380 Digital Logic

ECE380 Digital Logic ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For

More information

UNIT II. Circuit minimization

UNIT II. Circuit minimization UNIT II Circuit minimization The complexity of the digital logic gates that implement a Boolean function is directly related to the complexity of the algebraic expression from which the function is implemented.

More information

Module -7. Karnaugh Maps

Module -7. Karnaugh Maps 1 Module -7 Karnaugh Maps 1. Introduction 2. Canonical and Standard forms 2.1 Minterms 2.2 Maxterms 2.3 Canonical Sum of Product or Sum-of-Minterms (SOM) 2.4 Canonical product of sum or Product-of-Maxterms(POM)

More information

Gate Level Minimization

Gate Level Minimization Gate Level Minimization By Dr. M. Hebaishy Digital Logic Design Ch- Simplifying Boolean Equations Example : Y = AB + AB Example 2: = B (A + A) T8 = B () T5 = B T Y = A(AB + ABC) = A (AB ( + C ) ) T8 =

More information

CSE 140: Logic Minimization Lecture

CSE 140: Logic Minimization Lecture CSE 140: Logic Minimization Lecture What is Logic Minimization? Input: A set of minterms corresponding to a function F Output: A minimal set of prime implicants that corresponds to function F Example:

More information

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map

CSCI 220: Computer Architecture I Instructor: Pranava K. Jha. Simplification of Boolean Functions using a Karnaugh Map CSCI 22: Computer Architecture I Instructor: Pranava K. Jha Simplification of Boolean Functions using a Karnaugh Map Q.. Plot the following Boolean function on a Karnaugh map: f(a, b, c, d) = m(, 2, 4,

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard

More information

4 KARNAUGH MAP MINIMIZATION

4 KARNAUGH MAP MINIMIZATION 4 KARNAUGH MAP MINIMIZATION A Karnaugh map provides a systematic method for simplifying Boolean expressions and, if properly used, will produce the simplest SOP or POS expression possible, known as the

More information

Specifying logic functions

Specifying logic functions CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last

More information

Simplification of Boolean Functions

Simplification of Boolean Functions COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean

More information

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map

Points Addressed in this Lecture. Standard form of Boolean Expressions. Lecture 4: Logic Simplication & Karnaugh Map Points Addressed in this Lecture Lecture 4: Logic Simplication & Karnaugh Map Professor Peter Cheung Department of EEE, Imperial College London Standard form of Boolean Expressions Sum-of-Products (SOP),

More information

Combinational Logic & Circuits

Combinational Logic & Circuits Week-I Combinational Logic & Circuits Spring' 232 - Logic Design Page Overview Binary logic operations and gates Switching algebra Algebraic Minimization Standard forms Karnaugh Map Minimization Other

More information

Chapter 3. Gate-Level Minimization. Outlines

Chapter 3. Gate-Level Minimization. Outlines Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level

More information

Combinational Logic Circuits

Combinational Logic Circuits Chapter 2 Combinational Logic Circuits J.J. Shann (Slightly trimmed by C.P. Chung) Chapter Overview 2-1 Binary Logic and Gates 2-2 Boolean Algebra 2-3 Standard Forms 2-4 Two-Level Circuit Optimization

More information

VLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007

VLSI System Design Part II : Logic Synthesis (1) Oct Feb.2007 VLSI System Design Part II : Logic Synthesis (1) Oct.2006 - Feb.2007 Lecturer : Tsuyoshi Isshiki Dept. Communications and Integrated Systems, Tokyo Institute of Technology isshiki@vlsi.ss.titech.ac.jp

More information

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER

Gate-Level Minimization. BME208 Logic Circuits Yalçın İŞLER Gate-Level Minimization BME28 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com Complexity of Digital Circuits Directly related to the complexity of the algebraic expression we use to

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

Gate-Level Minimization. section instructor: Ufuk Çelikcan

Gate-Level Minimization. section instructor: Ufuk Çelikcan Gate-Level Minimization section instructor: Ufuk Çelikcan Compleity of Digital Circuits Directly related to the compleity of the algebraic epression we use to build the circuit. Truth table may lead to

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS)

DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) DIGITAL CIRCUIT LOGIC UNIT 5: KARNAUGH MAPS (K-MAPS) 1 Learning Objectives 1. Given a function (completely or incompletely specified) of three to five variables, plot it on a Karnaugh map. The function

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883

More information

Gate Level Minimization Map Method

Gate Level Minimization Map Method Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically

More information

Chapter 2 Combinational

Chapter 2 Combinational Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic

More information

IT 201 Digital System Design Module II Notes

IT 201 Digital System Design Module II Notes IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.

More information

Slides for Lecture 15

Slides for Lecture 15 Slides for Lecture 5 ENEL 353: Digital Circuits Fall 203 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary October, 203 ENEL 353 F3 Section

More information

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10

Literal Cost F = BD + A B C + A C D F = BD + A B C + A BD + AB C F = (A + B)(A + D)(B + C + D )( B + C + D) L = 10 Circuit Optimization Goal: To obtain the simplest implementation for a given function Optimization is a more formal approach to simplification that is performed using a specific procedure or algorithm

More information

Chapter 6. Logic Design Optimization Chapter 6

Chapter 6. Logic Design Optimization Chapter 6 Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is

More information

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 2016/2017

DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 2016/2017 27.2.2. DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 2. LECTURE: LOGIC NETWORK MINIMIZATION 26/27 2. LECTURE: CONTENTS. Canonical forms of Boolean functions

More information

WWW-BASED BOOLEAN FUNCTION MINIMIZATION

WWW-BASED BOOLEAN FUNCTION MINIMIZATION Int. J. Appl. Math. Comput. Sci., 2003, Vol. 13, No. 4, 577 583 WWW-BASED BOOLEAN FUNCTION MINIMIZATION SEBASTIAN P. TOMASZEWSKI, ILGAZ U. CELIK GEORGE E. ANTONIOU BAE SYSTEMS Controls 600 Main Street,

More information

Chapter 2 Combinational Logic Circuits

Chapter 2 Combinational Logic Circuits Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show

More information

ESE535: Electronic Design Automation. Today. EDA Use. Problem PLA. Programmable Logic Arrays (PLAs) Two-Level Logic Optimization

ESE535: Electronic Design Automation. Today. EDA Use. Problem PLA. Programmable Logic Arrays (PLAs) Two-Level Logic Optimization ESE535: Electronic Design Automation Day 18: March 25, 2013 Two-Level Logic-Synthesis Today Two-Level Logic Optimization Problem Behavioral (C, MATLAB, ) Arch. Select Schedule RTL FSM assign Definitions

More information

The Pythagorean Theorem: Prove it!!

The Pythagorean Theorem: Prove it!! The Pythagorean Theorem: Prove it!! 2 2 a + b = c 2 The following development of the relationships in a right triangle and the proof of the Pythagorean Theorem that follows were attributed to President

More information

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

More information

TWO-LEVEL COMBINATIONAL LOGIC

TWO-LEVEL COMBINATIONAL LOGIC TWO-LEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms To-level simplification Boolean cubes Karnaugh maps Quine-McClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and

More information

Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION

Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION Switching Theory And Logic Design UNIT-II GATE LEVEL MINIMIZATION Two-variable k-map: A two-variable k-map can have 2 2 =4 possible combinations of the input variables A and B. Each of these combinations,

More information

CS470: Computer Architecture. AMD Quad Core

CS470: Computer Architecture. AMD Quad Core CS470: Computer Architecture Yashwant K. Malaiya, Professor malaiya@cs.colostate.edu AMD Quad Core 1 Architecture Layers Building blocks Gates, flip-flops Functional bocks: Combinational, Sequential Instruction

More information

ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms

ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms ECE 5745 Complex Digital ASIC Design Topic 12: Synthesis Algorithms Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5745 RTL to

More information

Gate-Level Minimization

Gate-Level Minimization MEC520 디지털공학 Gate-Level Minimization Jee-Hwan Ryu School of Mechanical Engineering Gate-Level Minimization-The Map Method Truth table is unique Many different algebraic expression Boolean expressions may

More information

Contents. Chapter 3 Combinational Circuits Page 1 of 34

Contents. Chapter 3 Combinational Circuits Page 1 of 34 Chapter 3 Combinational Circuits Page of 34 Contents Contents... 3 Combinational Circuits... 2 3. Analysis of Combinational Circuits... 2 3.. Using a Truth Table... 2 3..2 Using a Boolean unction... 4

More information

Combinational Logic Circuits

Combinational Logic Circuits Chapter 3 Combinational Logic Circuits 12 Hours 24 Marks 3.1 Standard representation for logical functions Boolean expressions / logic expressions / logical functions are expressed in terms of logical

More information

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 5. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary Slide Set 5 for ENEL 353 Fall 207 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 207 SN s ENEL 353 Fall 207 Slide Set 5 slide

More information

MUX using Tri-State Buffers. Chapter 2 - Part 2 1

MUX using Tri-State Buffers. Chapter 2 - Part 2 1 MUX using Tri-State Buffers Chapter 2 - Part 2 Systematic Simplification A Prime Implicant is a product term obtained by combining the maximum possible number of adjacent squares in the map into a rectangle

More information

ADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS

ADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS ABSTRACT ADAPTIVE MAP FOR SIMPLIFYING BOOLEAN EXPRESSIONS Dr. Mohammed H. AL-Jammas Department of Computer and Information Engineering, College of Electronics Engineering, University of Mosul, Mosul -

More information

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.

Department of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals. Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR

More information

10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS QUESTION BANK 10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)

Final Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours) Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS

More information

數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷

數位系統 Digital Systems 朝陽科技大學資工系. Speaker: Fuw-Yi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷 數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: Fuw-Yi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,

More information

Supplement to. Logic and Computer Design Fundamentals 4th Edition 1

Supplement to. Logic and Computer Design Fundamentals 4th Edition 1 Supplement to Logic and Computer esign Fundamentals 4th Edition MORE OPTIMIZTION Selected topics not covered in the fourth edition of Logic and Computer esign Fundamentals are provided here for optional

More information

2.1 Binary Logic and Gates

2.1 Binary Logic and Gates 1 EED2003 Digital Design Presentation 2: Boolean Algebra Asst. Prof.Dr. Ahmet ÖZKURT Asst. Prof.Dr Hakkı T. YALAZAN Based on the Lecture Notes by Jaeyoung Choi choi@comp.ssu.ac.kr Fall 2000 2.1 Binary

More information

Giovanni De Micheli. Integrated Systems Centre EPF Lausanne

Giovanni De Micheli. Integrated Systems Centre EPF Lausanne Two-level Logic Synthesis and Optimization Giovanni De Micheli Integrated Systems Centre EPF Lausanne This presentation can be used for non-commercial purposes as long as this note and the copyright footers

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative

More information

CSE241 VLSI Digital Circuits UC San Diego

CSE241 VLSI Digital Circuits UC San Diego CSE241 VLSI Digital Circuits UC San Diego Winter 2003 Lecture 05: Logic Synthesis Cho Moon Cadence Design Systems January 21, 2003 CSE241 L5 Synthesis.1 Kahng & Cichy, UCSD 2003 Outline Introduction Two-level

More information

Gate-Level Minimization

Gate-Level Minimization Gate-Level Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method

More information

INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator

INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR Stamp / Signature of the Invigilator EXAMINATION ( Mid Semester ) SEMESTER ( Spring ) Roll Number Section Name Subject Number C S 2 1 0 0 2 Subject Name Switching

More information

Chapter 2. Boolean Expressions:

Chapter 2. Boolean Expressions: Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean

More information

ICS 252 Introduction to Computer Design

ICS 252 Introduction to Computer Design ICS 252 Introduction to Computer Design Logic Optimization Eli Bozorgzadeh Computer Science Department-UCI Hardware compilation flow HDL RTL Synthesis netlist Logic synthesis library netlist Physical design

More information

University of Technology

University of Technology University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows

More information

GATE Exercises on Boolean Logic

GATE Exercises on Boolean Logic GATE Exerces on Boolean Logic 1 Abstract Th problem set has questions related to Boolean logic and gates taken from GATE papers over the last twenty years. Teachers can use the problem set for courses

More information

Experiment 3: Logic Simplification

Experiment 3: Logic Simplification Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed El-Saied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions

More information

Boolean Function Simplification

Boolean Function Simplification Universit of Wisconsin - Madison ECE/Comp Sci 352 Digital Sstems Fundamentals Charles R. Kime Section Fall 200 Chapter 2 Combinational Logic Circuits Part 5 Charles Kime & Thomas Kaminski Boolean Function

More information

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN

NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary

More information

Introduction to synthesis. Logic Synthesis

Introduction to synthesis. Logic Synthesis Introduction to synthesis Lecture 5 Logic Synthesis Logic synthesis operates on boolean equations and produce optimized combinational logic Logic Minimization Two-level logic minimization Two-level logic

More information

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology

LSN 4 Boolean Algebra & Logic Simplification. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology LSN 4 Boolean Algebra & Logic Simplification Department of Engineering Technology LSN 4 Key Terms Variable: a symbol used to represent a logic quantity Compliment: the inverse of a variable Literal: a

More information

1.4 Euler Diagram Layout Techniques

1.4 Euler Diagram Layout Techniques 1.4 Euler Diagram Layout Techniques Euler Diagram Layout Techniques: Overview Dual graph based methods Inductive methods Drawing with circles Including software demos. How is the drawing problem stated?

More information

Digital Logic Design. Outline

Digital Logic Design. Outline Digital Logic Design Gate-Level Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR

More information

Introduction to Programmable Logic Devices (Class 7.2 2/28/2013)

Introduction to Programmable Logic Devices (Class 7.2 2/28/2013) Introduction to Programmable Logic Devices (Class 7.2 2/28/2013) CSE 2441 Introduction to Digital Logic Spring 2013 Instructor Bill Carroll, Professor of CSE Today s Topics Complexity issues Implementation

More information

BCNF. Yufei Tao. Department of Computer Science and Engineering Chinese University of Hong Kong BCNF

BCNF. Yufei Tao. Department of Computer Science and Engineering Chinese University of Hong Kong BCNF Yufei Tao Department of Computer Science and Engineering Chinese University of Hong Kong Recall A primary goal of database design is to decide what tables to create. Usually, there are two principles:

More information

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

More information

Combinational hazards

Combinational hazards Combinational hazards We break down combinational hazards into two major categories, logic hazards and function hazards. A logic hazard is characterized by the fact that it can be eliminated by proper

More information

Digital Logic Design (CEN-120) (3+1)

Digital Logic Design (CEN-120) (3+1) Digital Logic Design (CEN-120) (3+1) ASSISTANT PROFESSOR Engr. Syed Rizwan Ali, MS(CAAD)UK, PDG(CS)UK, PGD(PM)IR, BS(CE)PK HEC Certified Master Trainer (MT-FPDP) PEC Certified Professional Engineer (COM/2531)

More information

Unit-IV Boolean Algebra

Unit-IV Boolean Algebra Unit-IV Boolean Algebra Boolean Algebra Chapter: 08 Truth table: Truth table is a table, which represents all the possible values of logical variables/statements along with all the possible results of

More information

Chapter 2 Part 5 Combinational Logic Circuits

Chapter 2 Part 5 Combinational Logic Circuits Universit of Wisconsin - Madison ECE/Comp Sci 352 Digital Sstems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 2 Part 5 Combinational Logic Circuits Originals b: Charles R. Kime and Tom

More information

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map.

To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using Karnaugh Map. 3.1 Objectives To write Boolean functions in their standard Min and Max terms format. To simplify Boolean expressions using. 3.2 Sum of Products & Product of Sums Any Boolean expression can be simplified

More information

Ch. 5 : Boolean Algebra &

Ch. 5 : Boolean Algebra & Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying

More information

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps

Outcomes. Unit 9. Logic Function Synthesis KARNAUGH MAPS. Implementing Combinational Functions with Karnaugh Maps .. Outcomes Unit I can use Karnaugh maps to synthesize combinational functions with several outputs I can determine the appropriate size and contents of a memory to implement any logic function (i.e. truth

More information

McGILL UNIVERSITY Electrical and Computer Engineering Department MIDTERM EXAM

McGILL UNIVERSITY Electrical and Computer Engineering Department MIDTERM EXAM McGILL UNIVERSITY Electrical and Computer Engineering Department ECSE-323 DIGITAL SYSTEM DESIGN MIDTERM EXAM Winter 2010 Question Maximum Points Points Attained 1 15 2 10 3 10 4 15 5 20 6 5 Total 75 Please

More information

Lesson 10: Special Relationships within Right Triangles Dividing into Two Similar Sub-Triangles

Lesson 10: Special Relationships within Right Triangles Dividing into Two Similar Sub-Triangles : Special Relationships within Right Triangles Dividing into Two Similar Sub-Triangles Learning Targets I can state that the altitude of a right triangle from the vertex of the right angle to the hypotenuse

More information

EE 214 Lab 7 Computer-Based Minimization Tools Page 1/8

EE 214 Lab 7 Computer-Based Minimization Tools Page 1/8 EE 214 Lab 7 Computer-Based Minimization Tools Page 1/8 Overview NAME: SECTION: Logic functions can be described using behavioral descriptions or structural descriptions. Behavioral descriptions, such

More information

Type of Triangle Definition Drawing. Name the triangles below, and list the # of congruent sides and angles:

Type of Triangle Definition Drawing. Name the triangles below, and list the # of congruent sides and angles: Name: Triangles Test Type of Triangle Definition Drawing Right Obtuse Acute Scalene Isosceles Equilateral Number of congruent angles = Congruent sides are of the congruent angles Name the triangles below,

More information

9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A

9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a

More information

February Regional Geometry Team: Question #1

February Regional Geometry Team: Question #1 February Regional Geometry Team: Question #1 A = area of an equilateral triangle with a side length of 4. B = area of a square with a side length of 3. C = area of a regular hexagon with a side length

More information

Two-Level Logic Optimization ( Introduction to Computer-Aided Design) School of EECS Seoul National University

Two-Level Logic Optimization ( Introduction to Computer-Aided Design) School of EECS Seoul National University Two-Level Logic Optimization (4541.554 Introduction to Computer-Aided Design) School of EECS Seoul National University Minimization of Two-Level Functions Goals: Minimize cover cardinality Minimize number

More information

Chapter 2 QUIZ. Section 2.1 The Parallel Postulate and Special Angles

Chapter 2 QUIZ. Section 2.1 The Parallel Postulate and Special Angles Chapter 2 QUIZ Section 2.1 The Parallel Postulate and Special Angles (1.) How many lines can be drawn through point P that are parallel to line? (2.) Lines and m are cut by transversal t. Which angle corresponds

More information