1 Discussion. 2 Pre-Lab

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1 CSE 275 Digital Design Lab Lab 3 Implementation of a Combinational Logic Circuit Penn State Erie, The Behrend College Fall Semester 2007 Number of Lab Periods: 1 1 Discussion The purpose of this lab is to design, simulate, and implement a simple combinational logic circuit from its description. In this case, we will design and build a circuit that determines the result of a vote taken by a group of people. You will use Xilinx ISE and ModelSim to enter and simulate the circuit. Then, we will learn how to download the circuit to a target board and test the designed circuit. As a target hardware platform, the Programmable Logic Device Trainer board, PLDT-3, by R.S.R Electronics Company will be used. 2 Pre-Lab The PLDT-3 board features a Complex Programmable Logic Device, XC95108, made by Xilinx Corporation. The CPLDs will be used in the CSE275 as the target hardware, so you should become familiar with this technology. The XC95108 CPLD chip contains 108 microcells with 2400 usable gates arranged in six 36V18 function blocks. To learn more about the CPLDs, you can read the following document To learn more on the PLDT-3 trainer board visit the webpage of R.S.R. Electronics, Inc. at For this exercise, address the following problem: A committee consists of three members called A, B, and C. The meeting room of the committee has three switches by which each member can cast his/her vote. That is, if the switch is turned on to indicate a yes vote, logic level 1 is placed on the corresponding signal wire. A no vote corresponds to logic level 0 on the line instead. A circuit is needed which takes the three votes from the members as input and outputs a PASS signal which has logic 1 if the majority of the votes are for an issue and a FAIL signal which has logic 1 if not. The PASS and FAIL signals will be sent to LEDs to show if the vote has passed or failed. Create a truth table showing the correct values of the output signals (PASS and FAIL) for each combination of the inputs (A, B, and C). Write the canonical-form SOP Boolean equation for the PASS output signal in terms of the inputs. Reduce this equation to a simpler SOP form using Boolean algebra (do not use a K-map). Use DeMorgan s theorem to convert the equation for PASS into a form that makes it easier to implement using NAND gates (clue: a+b = (a b ) ). 1

2 Note that FAIL is just an inversion of PASS. Design (i.e. draw a schematic diagram for) the vote circuit using only NAND gates and inverters. 3 In-lab Task A Create a new Xilinx ISE project for this exercise and input your vote circuit from the prelab. Save the schematic diagram under the name VOTE. Use the ModelSim simulator to verify, for all possible combinations of inputs, that the circuit is working correctly. Task B Now we learn how to download the vote circuit to the PLDT-3 board and test the circuit. (1) If you look at the PLDT-3 board, you will find the red LEDs and the toggle switches S6 and S7, which are located on the bottom of the board. We will assign A, B and C to the toggle switches S6-1, S6-2 and S6-3 and the output signals PASS and FAIL to the leftmost two red LEDs 9 and 10. For the XC95108 CPLD chip, the pin connections with the switch S6, S7 and the red LEDs are listed in Table1. In our circuit, the inputs A, B, and C will use pins 11, 7 and 6, and the outputs PASS and FAIL will go to pins 35 and 36. Table 1 Pin Layout of Switches S6 and S7 and Red LEDs SWITCH CPLD PIN RED LEDs CPLD PIN S S S S S S S S (2) To make the pin assignments, we need to go back to the VOTE schematic. First, let us assign the pin 11 for input A. Double-click on the ibuf for input A. (NOTICE, IT IS IBUF, NOT I/O MARKER.) The Object Properties window (Figure 1) will appear. Click on the New button, which brings the New Attribute window. In that window, enter loc for Attribute Name and p11 for Attribute Value (Figure2). Then, click the OK button. Remember: the entries are not case sensitive. 2

3 Figure 1 The Object Properties window for ibuf. (3) You should now be back at the Object Properties window. Note that the entries you typed in the New Attribute window are reflected in the Object Properties window under Name and Value (Figure 3). Click on the OK button. Figure 2 Type pin number in the New Attribute window Figure 3 The Object Properties window after step 2. 3

4 Figure 4 Processes for Current Source pane after step 6. (4) The term loc =p11 should appear on the ibuf symbol. You can move it above the symbol by dragging it with your mouse. Repeat the same procedure to assign pin numbers p7, p6, p35 and p36 for the ibufs and obufs for B, C, PASS and FAIL. (5) Save your schematic and check errors by choosing Tool Check Schematic (If there are any errors in your schematic, click on the Help button and the error message will be displayed). Then, save the schematic diagram and select File Exit to close the Xilinx ECS window. (6) Next, we need to synthesize and implement your schematic design. Select VOTE in the Source in Project pane and then double-click on Generate Programming File. In this way, Synthesize and Implement Design will be done automatically before the programming file is generated. Expand the items in the Processes for Source pane by clicking the plus signs (+) next to them. The pane should now look similar to Figure 4. A green checkmark in the Processes for Source indicates that the process was run successfully. A yellow exclamation mark represents a warning for the process that was run. If you see a red X- mark, it means that there are errors in your design. You can find the error descriptions in the bottom pane of the window. (7) Connect the AC adaptor to your target board and plug it into an outlet. Then connect your PC to the target board with the parallel cable. Pull off all of eight jumpers from HD7. (8) To download the program into your CPLD, double-click on Configure Device (im- PACT) in the Processes for Source pane. Select Boundary Scan Automatically connect to cable and identify Boundary-Scan chain. You should see the impact window shown in Figure 5. 4

5 Figure 5 The impact window (9) Now, double-click on the Xilinx chip box in the impact window and select VOTE.jed and click open. Then the question mark for the file -- File? -- below the Xilinx chip box will be replaced by the file s name, VOTE.jed. (10) Right-click on the Xilinx chip in the impact window. In the pull-down menu that appears next, choose Program. In the Program Options windows, make sure that only Erase Before Programming is checked. Then click on the OK button. The programming should go on for about 5 to 15 second depending on the speed of your PC and the complexity of the circuit. To the end, you will see the message Programming Succeeded shown on the message window. (11) Plug in the eight jumpers to HD7 and verify that your circuit is working properly using the toggle switches S6-1, S6-2 and S6-3 to generate the values for A, B, and C while checking the LEDs to see if they display PASS and FAIL at the correct times. 4 Lab Report In the results of your report, include the truth table for the desired operation of your circuit and your final Boolean equation for PASS. Include hard copies of the Xilinx ISE schematic for the circuit that you designed to implement the equation and the result of the simulation waveform that confirms its operation. Give some explanation as to what problems you encountered and any trouble-shooting you had to do to obtain the correct results. 5

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