Computer Organization

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1 A Text Book of Computer Organization and Architecture Prof. JATINDER SINGH Director, GGI, Dhaliwal Er. AMARDEEP SINGH M.Tech (IT) AP&HOD, Deptt.of CSE, SVIET, Banur Er. GURJEET SINGH M.Tech (CSE) Head, Deptt. of Computer Science SGHS Khalsa College for Women, Mattewal-Amritsar UDH Publishers & Distributors (P) Ltd.

2 Contents Preface Acknowledgments xi xiii Boolean Algebra Introduction Difference between Boolean Algebra and Switching Algebra Binary Valued Quantities and Bistable Devices What is a Truth Table? The Principle of Duality Duality Theorem Canonical Forms for Boolean Function Karnaugh Map (K Map) Logic Gates Derived Gates Combinational Circuit Sequential Circuits Digital Components Half Adder and Full Adder Parallel Binary Adders Subtraction Encoders and Decoders Decoder 41 Exercise 44 Computer System Architecture Introduction What is Computer Architecture? Structural Hierarchy Computer Organization Vs Computer Architecture Computer Systems General Computer System Architecture IPO (Input-Process-Output) Model Operations on Digital Process Detailed Computer System Organization/Computer Architecture Elements of Computer System 55

3 vi A Text Book of Computer Organization and Architecture 2.11 Software Types of Computers 2.13 Milestones in Computer Architecture Basic Computer Architectures Basic Computer Organization Simplified Computer Architecture Design Levels Combinational or Sequential Design Measuring Computer Performance System Performance The Moore's Law 66 Exercise Combinational and Sequential Circuits Introduction Combinational Circuits Decoders Encoders Multiplexers (MUX) Demultiplexer Sequential Circuits Flip-flops Edge-Triggered Flip-flops Pulse-Triggered (Master-Slave) Flip-flops Registers Counters Memory Unit, RAM, ROM 88 Exercise Data Represetation Introduction Number Systems Decimal Numbers Binary Numbers Octal Numbers Hexadecimal Numbers Binary Number Formats More About Binary Numbers Binary Arithmetic Overview of Hexadecimal Arithmetic Signed and Unsigned Binary Numbers Addition and Subtraction Operations with Signed Binary Range of Signed and Unsigned Binary Numbers 115 Exercise 115

4 Contents vii 5. Register Transfer and Microoperations Introduction Register Transfer Language Register Transfer Bus and Memory Transfer Three-State Bus Buffers Memory Transfer Arithmetic Microoperations Logic Microoperations Shift microoperations Arithmetic Logic Shift Unit Hardware Description Languages 135 Exercise Basic Organization and Design Introduction Memory Organization Instruction Codes Computer Registers Computer Instructions Timing and Control Instruction Cycle Memory Reference Instructions Input-Output and Interrupt Complete Computer Description Design of Basic Computer Design of Accumulator Logic 168 Exercise Central Processing Unit Central Processing Unit Processor Design Instruction Set Architecture Internal Storage in CPU General Purpose Register Organization Single Accumulator Organization Stack Organization Memory Stack Reverse Polish Notation Instruction Formats What is an Instruction Format Three-Address Instruction Format Two-address Instructions Format One-Address Instructions Format 195

5 viii A Text Book of Computer Organization and Architecture 7.15 Zero-Address Instruction Format Addressing Modes 197 Exercise 204 Input Output Organization Input 8Devices Output Devices Audio Devices System Components System Buses Synchronous Data Transfers Asynchronous Data Transfers I/O Modules Interface Modules I/O and Memory Buses Interrupts Types of Interrupts Advantages of Interrupts Uses of Interrupts DMA (Direct Memory Access) Input/Output Processor Input/Output Channels 222 Exercise Memory Organization Introduction Memory Hierarchies Characteristics of the Memory Hierarchy Secondary Storage Self-Monitoring, Analysis and Reporting Technology System Organization of Data on a Hard Drive RAM Primary Memory Organization of Memory Devices Interfacing Memory to a Processor 243 Exercise Cache and Virtual Memory Introduction Cache Organization Cache Operation Cache Write Policy Registers Virtual Memory Paging and Segmentation 263

6 Contents ix 10.8 Detailed Description of Virtual memory Translation Lookaside Buffer Segmentation Combined Paging and Segmentation Maintaining Track of Free Memory Page replacement Algorithms NRU (Not Recently Used) Algorithm 272 Exercise 273 Parallel Processing 274 li.l Introduction Flynn's Classification Pipelining Array Processor/Vector Processor Interprocessor Communication and Synchronization Multiprocessor Symmetric Multi-Processor (SMP) Super Scalar Processor VUW Architecture Super Computers Pentium Server System 322 Exercise 324 Glossary 326 Index 339

Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore

COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. Radhakrishnan Professor of Computer Science