Embedded Systems: Architecture
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1 Embedded Systems: Architecture Jinkyu Jeong Computer Systems Laboratory Sungkyunkwan University ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong
2 Designing Embedded Systems Requirements Specification Architecture Component Design System Integration ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 2
3 Basic Architectures ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong
4 Control Unit Custom logic FPGAs (Field-Programmable Gate Arrays) Microcontrollers Microprocessors DSPs (Digital Signal Processors) ASIPs (Application Specific Instruction-set Processors) Multicore? (symmetric vs. asymmetric) Typical word size: 8/16/32-bit ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 4
5 Why Microprocessors? Microprocessors ARM, MIPS, PowerPC, SuperH, Cell, Atom, Mostly less than 1 GHz Microprocessors are often very efficient Can use same logic to perform many different functions Microprocessors simplify the design of families of products ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 5
6 The Performance Paradox Microprocessors use much more logic to implement a function than does custom logic But microprocessors are often at least as fast: Heavily pipelined Large design teams Aggressive VLSI technology, ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 6
7 Power Custom logic uses less power, but CPUs have advantages Modern microprocessors offer features to help control power consumption Software design techniques can help reduce power consumption Heterogeneous systems Some custom logic for well-defined functions, CPUs + software for everything else ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 7
8 RAM SRAM Easier to integrate on the same chip as processor DRAM SDRAM (Synchronous DRAM): SDR/DDR/DDR2/DDR3 Mobile SDR/DDR SDRAM RDRAM (Rambus DRAM) NVRAM (Non-Volatile RAM) Future NVRAMs: PRAM, MRAM, FeRAM Cache memory SPM (Scratch Pad Memory) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 8
9 ROM Mask-programmed Connections programmed at fabrication OTP (One-time programmable) ROM Connections programmed after manufacture by user EPROM (Erasable programmable ROM) EEPROM (Electrically erasable programmable ROM) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 9
10 Flash Memory NOR Flash NAND Flash e-mmc UFS Cards (MMC, SD, CF, ) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 10
11 Interfacing ARM AMBA (Advanced Microcontroller Bus Architecture) ISA (Industry Standard Architecture) PCI (Peripheral Component Interconnect) I 2 C (Inter-IC) bus USB ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 11
12 Common Peripheral Devices Interrupt controller DMA controller Timer/Counter Real-time clock Watchdog timer UART (Universal Asynchronous Receiver Transmitter) IrDA (Infrared) Ethernet (wired/wireless) Bluetooth ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 12
13 Recent Trends Increasing computation demands Increasingly networked Increasing need for flexibility Getting complex Increasingly platform-based Hardware architecture + associated software ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 13
14 SoC (System-On-a-Chip) Samsung Exynos 7420 Source: ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 14
15 Introduction to the ARM Architecture ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong
16 Overview (1) Advanced RISC Machine The most widely used 32-bit ISA 98% of the more than 1 billion mobile phones sold used at least one ARM processor (2005) 4 billion shipped in % of all embedded 32-bit RISC processors (2009) ARM architecture has been extended over several versions. ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 16
17 Overview (2) ARM processors developed by licensees DEC StrongARM Marvell (formerly Intel) Xscale Nintendo TI OMAP Qualcomm Snapdragon Samsung Hummingbird/Exynos Apple A4/A5/A5X/A6/A7 Nvidia Tegra Applied Micro X-Gene ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 17
18 ARM Design Goals High performance Small code size Low power consumption Small silicon area ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 18
19 Application Processors Galaxy S4 (quad-core 1.6GHz + quad-core 1.2GHz Cortex-A7) iphone 4S (dual-core, 800MHz) ipad 2 (dual-core, 1GHz) New ipad (dual-core, 1GHz) Galaxy S2 (dual-core, 1.2GHz) Galaxy S3 (quad-core, 1.4GHz) iphone 3GS (600MHz) iphone 4 (clock speed not disclosed, 800MHz?) ipad (1GHz) Samsung Galaxy S (1GHz) Samsung Galaxy Tab 7 (1GHz) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 19
20 Embedded Processors ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 20
21 Processors Lineup ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 21
22 ARM 7TDMI-S Synthesizable core Thumb Debug Multiplier ICE Implements the ARMv4T architecture Applications ipod from Apple Nintendo DS & Game Boy Advance Most of Nokia s mobile phones Lego Mindstorms NXT iriver portable digital audio players Roomba 500 series from irobot ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 22
23 Thumb Instruction Sets 16-bit instruction set A subset of the most commonly used 32-bit ARM instructions Significantly improved code density at a cost of some reduction in performance Typically 65% of the ARM code size 160% performance of the ARM code when running from a 16-bit memory system Transparently decompressed to full 32-bit ARM instructions in real time, without performance loss ARM instructions only for performance critical segments ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 23
24 Memory Architectures ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong
25 Minimalist Approach Pros Simple, easy to design Cons Limited ROM size Limited SRAM size No firmware upgrades CPU SRAM (data) ROM (code) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 25
26 NOR XIP Pros Simple, easy to design Execute-In-Place (XIP) Predictable read latency Code + Storage in NOR Firmware upgrades Cons Slow read speed Much slower write speed The high cost of NOR CPU SDRAM (data) NOR (code) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 26
27 NOR Shadowing Pros Faster read and write Easy boot-up Use a relatively pricey NOR only to boot up the system Code can be compressed Cons Larger DRAM needed Require more design time Not energy efficient CPU SDRAM data code boot code NOR (code) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 27
28 NAND Shadowing Pros Faster read and write Cost effective NAND for both code and data storage Cons Require a special boot mechanism Extensive ECC for NAND Larger DRAM needed Require more design time Not energy efficient CPU SDRAM data code NAND (code) boot code NOR/ NAND/ EPROM ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu) 28
29 Hybrid NAND Shadowing Pros Much faster read and write speed ECC embedded Cost effective NAND for both code and data storage Cons Larger DRAM needed Not energy efficient CPU SDRAM data code OneNAND (code) ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 29
30 NAND Demand Paging Pros Less DRAM required Low cost Energy efficient NAND for both code and data storage Cons Require MMU-enabled CPU Unpredictable read latency Complex to design and test CPU data code NAND (code) boot code NAND/ EPROM ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong 30
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