Microcontrollers: Lecture 2 Low power Modes, Buses, Memory, GPIOs. Michele Magno

Transcription

1 Microcontrollers: Lecture 2 Low power Modes, Buses, Memory, GPIOs Michele Magno 1

2 Calendar : Power consumption; Low power States; Buses, Memory, GPIOs Interrupts, Timers, ADC, DAC Exercises Serial Communications Programming STM DMA / Interfacing external devices Sensors / Radios Projects presentation and exercises. 2

3 Outline MCU Architecture Power Consumption Frequency and voltage Low power modes Buses Memory GPIOs 3

4 Example of MCU Architecture Clock Memory ADC - DAC I/O Port CPU BUS DMA TIMERs USARTx 4

5 Performance Metrics How we compare and classify microcontrollers? Performance Metrics NOT easy to define and mostly application depended. Eletrical: Power Consumptions Voltage Supply Noise Immunity Sensitivity Goal: best tradeoff power consumptions Vs performances Computation: Clock Speed MIPS (instructions per sec) Latency Lateness of the response Lag between the begin and the end of the computation Throughput Tasks per second Byte per second 5

6 Power as a Design Constraint Why worry about power? Battery life in portable and mobile platforms Power consumption in desktops, server farms - Cooling costs, packaging costs, reliability, timing - Power density: 30 W/cm2 in Alpha (3x of typical hot plate) Where does power go in CMOS? Dynamic power consumption Power due to shortcircuit current during transition Power due to leakage current P ACV 2 f AVI short f VI leak 6

7 Dynamic Power Consumption C Total capacitance seen by the gate s outputs Function of wire lengths, transistor sizes,... V Supply voltage Trend: has been dropping with each successive fab ACV 2 f A - Activity of gates How often on average do wires switch? f clock frequency Trend: increasing... Reducing Dynamic Power 1) Reducing V has quadratic effect; Limits? 2) Lower C - shrink structures, shorten wires 3) Reduce switching activity - Turn off unused parts or use design techniques to minimize number of transitions 7

8 Short-circuit Power Consumption AVI short f Vin I short C L Vout Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting Reducing Short-circuit 1) Lower the supply voltage V 2) Slope engineering match the rise/fall time of the input and output signals 8

9 Leakage Power VI leak Sub-threshold current Sub-threshold current grows exponentially with increases in temperature and decreases in Vt 9

10 How can we reduce power consumption? Dynamic power consumption Reduce the rate of charge/discharge of highly loaded nodes Reduce spurious switching (glitches) Reduce switching in idle states (clock gating) Decrease frequency Decrease voltage (and frequency) Static power Consumption Smaller area (!) Reduce device leakage through power gating Reduce device leakage through body biasing Use higher-threshold transistors when possible Power performance tradeoffs! 10

11 Why Ultra-low Power Is so Important Longer battery life Smaller products Simpler power supplies Less EMI simplifies PCB Permanent battery Reduced liability 11

12 STM32L1x - Block Diagram 12 Frequency is plaining an important role For performance and Power Presentation Title

13 STM32F4 - clock features Four oscillators on board HSE (High Speed External Osc) 4..26MHz (can be bypassed by and ext. Oscillator) HSI (High Speed Internal RC): factory trimmed internal RC oscillator 16MHz +/- 1 LSI (Low Speed Internal RC): 32kHz internal RC used for IWDG, optionally RTC and AWU LSE (Low Speed External oscillator): kHz osc (can be bypassed by an external Osc) precise time base with very low power consumption (max 1µA). optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode. Two PLLs Main PLL (PLL) clocked by HSI or HSE used to generate the System clock (up to 168MHz), and 48 MHz clock for USB OTG FS, SDIO and RNG. PLL input clock in the range 1-2 MHz. PLLI2S PLL (PLLI2S) used to generate a clock to achieve HQ audio performance on the I 2 S interface. More security Clock Security System (CSS, enabled by software) to backup clock in case of HSE clock failure (HSI feeds the system clock) linked to Cortex NMI interrupt Spread Spectrum Clock Generation (SSCG, enabled by software) to reduce the spectral density of the electromagnetic interference (EMI) generated by the device

14 CSS STM32L1 an advanced system clock 14 The 5 clocks sources, the PLL and the CSS offers the maximum flexibility and safety for any battery-operated application. HSI 16 MHz High Speed Internal 16MHz. Multiplied by 2 using the PLL to reach the 32MHZ. User trimable with +/-0.5% accuracy MSI Internal 64kHz to 4MHz Multi-Speed Internal clock Very low frequency to address ultra-low-consumption budget application. LSI 38kHz Low Speed Internal clock (also called Security clock). Used for Watchdog security and RTC. HSE External 1-24MHz LSE 32kHz High Speed External clock: external quartz could be 1 to 24MHz. USB 48MHz clk will require only a 16MHz crystal(cheaper), x3 using PLL. You can still reached ultra-low-consumption value below 16MHz (down to 65KHz) In case of HSE failure Clock Security System (CSS) will switch to HSI. Low Speed External clock ( KHz) Mainly used for precise RTC. Could be used to calibrate HSI & MSI. LSE could also be calibrate by external clock (eg: 50Hz of Home power supply)

15 / 2, KHz HSE /2, to 31 OSC32_IN LSE OSc OSC32_OUT ~32KHz LSI RC OSCILLATORS! 16MHz HSI RC 4-26 MHz OSC_OUT HSE Osc OSC_IN VCO / P / Q x N / R IWDGCLK / M RTCCLK TIM5 IC4 HSI STM32F4 - clock scheme CSS SELECTION, APB1 HSE SYSCLK AHB Prescaler Prescaler /1,2 512 /1,2,4,8,16 PRESCALING PLLCLK 168 MHz & max SECURITY PLL48CLK (USB FS, SDIO & RNG) /8 SysTick APB2 Prescaler /1,2,4,8,16 PCLK1 up to 42MHz If (APB1 pres CLOCKS! =1) x1 TIMxCLK Else TIM2..7, x2 If (APB2 pres =1) x1 Else x2 HCLK up to 168MHz PCLK2 up to 84MHz TIMxCLK TIM1,8..11 PLL VCO / P MCO1 /1..5 EXT MCO2 /1..5 HSI HSE PLLCLK LSE SYSCLK HSE PLLCLK PLLI2S x N PLLI2S / Q / R PLLI2SCLK I2SCLK MACTXCLK MACRXCLK MACRMIICLK USB HS ULPI clock Ext. Clock I2S_CKIN Ethernet PHY USB2.0 PHY

16 Clocks 16 Osc/Clocks Speed Cons. Precision 25 C/0-85 C Wakeup HSE ext crystal 1-24 MHz ~500 µa ~0.01% (100ppm) 1ms HSE ext clock 1-32 MHz NA NA HSI 16 MHz 100 µa 1%/2.5% 3.7 µs MSI 65 khz-4.2 MHz µa 0.5%/3% 3.7 µs PLL 2-32 MHz 350 µa NA 100 µs LSI 37 khz 0.4 µa 50% 200 µs LSE ext crystal 32.7 khz typ 0.5 µa ~0.002%(20ppm) ~1s LSE ext clock khz NA NA

17 Clock Scheme 17 System Clock (SYSCLK) sources MSI HSI HSE PLL Configurable dividers provides AHB, APB1/2 and TIM clocks RTC / LCD Clock sources LSE LSI HSE clock divided by 2, 4, 8 or 16 Clock Security System (CSS) in case of HSE clock failure Interrupt linked to Cortex NMI USB Clock (USBCLK) provided from the internal PLL (PLLVCO/2) Clock-out capability on MCO pin

18 ADC Clocks 18 ADC digital interface was designed to operate in a completely independent manner, at its maximum speed using an internal 16 MHz clock source (HSI), whatever the CPU operating frequency (which can range from sub-khz up to 32 MHz). ADC APB2 clock (PCLK2) ADC Peripheral HSI (16 MHz) Digital Interface ADC Prescalers: /1, /2 and /4 ADCCLK Analog Interface

19 Peripheral Clock Gating 19 Clocking the peripheral increases consumption when the Bus clock is running So the clock driving each peripheral can be gated Default mode at reset is gated, minimizing consumption Peripheral can be gated automatically when entering Sleep mode Be aware of non-synchronous consumption though! (GPIO sink/source, etc) Consumption (ex: HD): range 1 range 2 range 3 LP Sleep / Run Condition: 32 MHz 16 MHz 4 MHz 65 khz GPIOA GPIOB CRC DMA FSMC SYSCFG & RI TIM TIM TIM TIM LCD WWDG USB PWR DAC ALL Value µa/mhz

20 20 Power Modes And Voltages Presentation Title

21 A practical example: STM32L1 Platform 21 Ultra-low-power and efficient with 1.65V to 3.6V VDD range Run on MSI CLK: 183 µa/mhz (Active mode) Run full speed (32 MHz): 249 µa/mhz with 2.61 CoreMark/MHz Run low-power (32 khz 137 khz): from 9 µa to 37 µa (down to 4.4 µa in Low-power Sleep) Additional 2 ultra-low-power modes Stop mode: down to 500 na (1.2 μa with RTC) Standby mode: down to 300 na (with POR, PDR, 3 wakeup pins and 20byte of backup RAM retention) Dynamic voltage scaling Maximum f CPU (MHz) µa/ DMIPS² µa/ DMIPS² µa/ DMIPS² 1.2 V 1.5 V 1.8 V V CORE Value given for V DD 25 C Execution from Flash 2/ Run from Flash with int. osc. at min values

22 Dynamic voltage scaling in Run mode 22 Voltage scaling optimizes the product efficiency (Consumption vs Performance) User selects a Range (voltage scaling) according to : External V DD Frequency (performance required) Wait state for Flash 22

23 Limitations depending on the power supply range 23 Operating power supply range ADC operation USB VCORE Maximum CPU frequency (fcpu max) V DD = 1.65 to 1.8V Not functional Not functional Range 2 or Range 3 16 MHz (1ws) 8 MHz (0ws) V DD = 1.8 to 2.0V Conversion time up to 500 Ksps Not functional Range 2 or Range 3 16 MHz (1ws) 8 MHz (0ws) V DD = 2.0 to 2.4V Conversion time up to 500 Ksps Functional * Range 1, Range 2 or Range 3 32 MHz (1ws) 16 MHz (0ws) V DD = 2.4 to 3.6V Conversion time up to 1 Msps Functional * Range 1, Range 2 or Range 3 32 MHz (1ws) 16 MHz (0ws) * requires range 1 + USB transceiver requires VDD>=3.V to be compliant 23

24 Limitations depending on V CORE 24 V CORE Maximum CPU frequency (Fcpu max) Programming Flash/EEPROM HSI HSE Max Maximum PLL frequency after Multiply ADC Clock max Range MHz to 4.2 MHz (1ws) 32 khz to 2.1 MHz (0ws) No Not for SYSCLK 4 MHz 24 MHz 4 MHz Range 2 8 MHz to 16 MHz (1ws) 32 khz to 8 MHz (0ws) Yes Yes 16 MHz 48 MHz 16 MHz Range 1 16 MHz to 32 MHz (1ws) 32 khz to 16 MHz (0ws) Yes Yes 32 MHz (clock) 24 MHz (crystal) 96 MHz 16 MHz

25 25 System Modes Presentation Title

26 System modes 26 RUN SLEEP:CPU stopped LPRUN: power regulator in LP mode LPSLEEP: power regulator in LP mode +CPU stopped STOP: power regulator in LP mode + all clock stopped STANDBY: power regulator stopped

27 Low-power modes transitions 35 LPSleep Sleep LPRun Shutdown Stop1 Run Standby Stop2 Reset

28 Typ current V DD Range STM32L1x Power profile 128 Kbytes Flash die µA/MHz 105 C 25 C 249µA/MHz 1 Full speed (32MHz) 12µA Wake up time Stop to Run: 8μs Standby to run: 50μs 183µA/MHz 1 MSI clock (4.2MHz) 9 µa 6.2µA 4.4 µa 2.7μA 1.2µA 2 500nA 3 1.4μA 900nA 2 300nA 3 Dynamic Run From Flash Low-Power 32KHz Low-Power Sleep KHz Stop w/ RTC or w/o RTC Standby 1/ Dhrystone power consumption value executed from Flash with V DD =3V 2/ Stop and standby with RTC given with V DD =1.8V 3/ Stop and standby without RTC given with V DD =3V

29 Typ current V DD Range STM32L1x Power profile 256 Kbytes Flash die µA/MHz 105 C 25 C 218µA/MHz 1 Full speed (32MHz) 12µA Wake up time Stop to Run: 8μs Standby to run: 50μs 162µA/MHz 1 MSI clock (4.2MHz) 11 µa 6.2µA 4.4 µa 2.7μA 1.5µA 2 630nA 3 1.4μA 1.3µA 2 350nA 3 Dynamic Run From Flash Low-Power 32KHz Low-Power Sleep KHz Stop w/ RTC or w/o RTC Standby 1/ Dhrystone power consumption value executed from Flash with V DD =3V 2/ Stop and standby with RTC given with V DD =1.8V 3/ Stop and standby without RTC given with V DD =3V

30 Interconnect Controller Down to LP Sleep mode 30 The IC provides autonomous communication between peripherals (independent from CPU and DMA). It offers fast and predictable latency. Available in Sleep or LP-Sleep mode (Wakeup time from sleep to run is 0.36μs!!) Z Z Z ARM Cortex-M3 Interconnect Trig Controller CH1 CH5 IC producer TIMERS (Trigger Out) TIMERS (CC event) RTC COMPARATORS OSCILLATORS IC Consumer TIMERS (Trigger In) DAC ADC TIMERS (Input Capture) TIMERS (OCREF clear)

31 STM32L1 pushing its limits Datasheet update(1/2) 31 Full 1.8V 3.6V V DD range 32 MHz Aggressive consumption in Stop mode (25 3.6V) with: Stop Mode: 0.57 μa Stop Mode + RTC: V Stop Mode + RTC: V Aggressive consumption in Standby mode (25 3.6V) with: Standby Mode: 0.3 μa Standby Mode + RTC: V Standby Mode + RTC: V Backup register retention (80Bytes) I/O leakage: 10nA

32 Low Power Modes: Sleep Mode 32 SLEEP Mode: Core stopped, peripherals kept running Entered from by executing special instructions WFI (Wait For Interrupt) Exit: Any peripheral interrupt WFE (Wait For Event) An event can be an interrupt enabled in the peripheral control register but NOT in the NVIC OR an EXTI line configured in event mode Exit: as soon as the event occurs No time wasted in interrupt entry/exit Two mechanisms to enter this mode Sleep Now: Enter SLEEP mode as soon as WFI or WFE is executed Sleep on Exit: Enter as soon as it exits the lowest priority ISR The stack is not popped before entering the sleep, it will not be pushed when the next interrupt occurs, saving running time

33 Low Power Modes: LPRUN 33 LP RUN Mode: Core running, peripherals kept running Entered by System Clock is set to multispeed internal (MSI) RC oscillator (131kHz max) Execution from SRAM or Flash memory Internal regulator is in low power mode to minimize the regulator's operating current FLASH can be in Power Down mode (when executing from RAM) VREFINT can be OFF The system clock frequency and enabled peripherals are both limited. Overall consumption of digital IP limited to 200µA When flash is in Power Down Mode, interrupts must be mapped to RAM (Vector Table Offset Register)

34 Low Power Modes: LPRUN 34 The current limitation in LPRun applies to the domain powered by the regulator The consumption of VDDA and IO supply is not specifically limited in this mode

35 Low Power Modes: LP Sleep (1/2) 35 LP sleep Mode: Core stopped, peripherals kept running Entered by executing special instructions from LPRUN mode WFI (Wait For Interrupt) WFE (Wait For Event) Internal regulator is in low power mode to minimize current draw FLASH can be in Power Down mode V REFINT can be OFF

36 Low Power Modes: STOP 36 STOP Mode: all peripheral clocks, PLL, MSI, HSI and HSE are disabled, SRAM and register contents are preserved. If the RTC, LCD and IWDG are running they are not stopped Voltage Regulator can be put in Low Power mode Wake-up sources: WFI was used for entry: any EXTI Line configured in Interrupt mode WFE was used for entry: any EXTI Line configured in event mode EXTI sources can be: one of the 16 GPIO lines, PVD, RTC sources, Comparators, USB wakeup After resuming from STOP, the clock config returns to its reset state (MSI used as system clock) Wake-up time from Stop mode on MSI RC at 4MHz STM32L15x typ Regulator in run or in low power mode mode (V REFINT ON) 7.9 µs Regulator in run or in low power mode mode (V REFINT OFF with Fast Wakeup) 7.9µs

37 Definition of Wake Up Time from STOP mode 37 Wake Up Time from STOP mode is defined here as from IT event to the interrupt vector fetch Wake Up time contributors: ANALOG delay : MSI start up : 3.5us REGULATOR switch from LP to MR mode : 3.5us (voltage range has an impact on the startup of the regulator / temperature also has an impact 6.5µs MAX) EEPROM start up : 3us MAX (after the ready of the regulator) DIGITAL delay System synchronization: 10 clock cycles Interrupt vector fetch / context restoring : 20 clock cycles Wake Up clock : Wakeup sequence is done on MSI and its frequency is the one selected before entering STOP mode. (max wakeup freq is 4.2MHz) Wake Up time in datasheet : 8.2µs typ / 9.3µs max (range 1 and range 2)

38 WakeUp from STOP Timing Diagram 38 WakeUp Event Analog WakeUp WakeUp Time MSI PD MSI READY MSI Clock MSI StartUp (3.5us MAX) 20 cycles MSI 4MHZ REG PD READY LP mode REG StartUp (3.5us MAX) MR mode REGULATOR EE PD EE READY IddQ mode EE wakeup (3us MAX) Operating mode EEPROM CPU CLK 6.5µs 2µs Interrupt vector fetch 1 st ISR word fetch start Analog delay 3 cycles 7 cycles 20 cycles

39 Low Power Modes: Standby 39 STANDBY Mode: V CORE domain is powered off and V REFINT can be OFF. SRAM and register contents are lost except registers in the STANDBY circuitry RTC and IWDG are kept running in STANDBY (if enabled) In STANDBY mode all IO pins are high impedance except Reset pad (still available) RTC_AF1 pin, if configured WKUP1, WKUP2 and WKUP3 pins if enabled Wake-up sources: WKUP1, WKUP2, WKUP3 pins rising edge RTC alarm A, RTC alarm B, RTC Wakeup, Tamper event, TimeStamp External reset in NRST pin IWDG reset After wake-up from STANDBY mode, program execution will restart in the same way as after a RESET. Wake-up time from STANDBY mode on MSI RC at 2MHz STM32L15x typ STANDBY with V REFINT ON 57.2 µs STANDBY with V REFINT OFF 2.4 ms

40 Standby Circuitry 40 Standby Circuitry contains Low power calendar RTC (Alarm, periodic wakeup) 80 Bytes Data RTC registers Separate 32KHz Osc (LSE) for RTC RCC CSR register: Clock + LSE config Standby Circuitry -> Reset only by RTC domain RESET Wakeup Pin 1 RCC CSR reg 32kHz OSC (LSE) Wakeup sources 3 wakeup pins (1 for MD) RTC Alarm A or AlarmB Wakeup Pin 3 RTC_AF1 Wakeup Pin 2 Wakeup Pin 2 Wakeup Logic LSI IWDG RTC Bytes Data RTC Wakeup Timer RTC Tamper / Timestamps Events RTC Alternate functions Tamper detection: resets all RTC user backup registers RTC Alarm Outputs: Alarms A/B, Wakeup on AF1 pin RTC Clock calibration Output

41 Typ current V DD Range CPU ON STM32L1x Power profile 256 Kbytes Flash die Peripherals activated RAM & context preserved Backup registers preserved µA/MHz 105 C 25 C 218µA/MHz 1 Full speed (32MHz) 12µA Wake up time Stop to Run: 8μs Standby to run: 50μs 162µA/MHz 1 MSI clock (4.2MHz) 11 µa 6.2µA 4.4 µa 2.7μA 1.5µA 2 630nA 3 1.4μA 1.3µA 2 350nA 3 Dynamic Run From Flash Low-Power 32KHz Low-Power Sleep KHz Stop w/ RTC or w/o RTC Standby

42 Overview RUN (Range1) at 80 MHz 120 µa / MHz** 3 RUN (Range2) at 26 MHz 100 µa / MHz** Wake-up time LPRUN at 2 MHz 112 µa / MHz** 6 cycles 6 cycles 4 µs 5 µs SLEEP at 26 MHz LPSLEEP at 2 MHz STOP 1 (full retention) STOP 2 (full retention) 35 µa / MHz 48 µa / MHz 6.6 µa / 6.9 µa* 1.1 µa / 1.4 µa* Application benefits High performance CoreMark score = 273 Outstanding power efficiency 14 µs STANDBY + 32 KB RAM 350 na / 650 na* ULPBbench score = µs STANDBY 115 na / 415 na* 256 µs SHUTDOWN 30 na / 330 na* VDD = C VBAT 4 na / 300 na* * : with RTC ** : from SRAM1

43 Low Power system design challenges

44 Introduction 45 The relation and balance between the performance and execution time needs to be carefully analyzed to find a best compromise which leads to lowest energy consumption. P T = Time of Period P = Activation Time Duty Cycling = (Activity Period/Time of Period) * 100% T

45 MCU Shootout 46 MCU A MCU B Active mode 2 ma 2.1 ma (+5%) Low power mode 1 ua 0.6 ua (-40%) Current or energy? And what about power profile? MCU A MCU B Energy (10% active in 1s interval) 10% Duty Cycling Energy (0.1% active in 1s interval) 0.1% Duty Cycling uj uj (+4,8%) 3 uj 2.7 uj (-10%)

46 Power versus Energy 47 What if the MCUs have different architectures and CoreMark scores? The time spent in active mode will not be equal. MCU A(16-bit) MCU B(32-bit) Active mode time 10 % 7 % Energy (in 1s) uj uj (-26.6 %) Less time spent in active lower total energy consumed. We can do so by using optimization techniques.

47 Use the compiler optimizations 48 optimization size of test code energy consumed in 1s max speed 5456 B 40.6 uj min size 3944 B 77.6 uj (+92%!) To reduce time spent in Active mode we have to select Speed Optimization compiler target

48 49 BUSES AND MEMORY Presentation Title

49 Processor vs. MCU

50 Harvard architecture Separate Instruction & Data buses enable parallel fetch & store Advanced 3-Stage Pipeline Includes Branch Forwarding & Speculation Additional Write-Back via Bus Matrix Pipeline

51 STM32 Value line 64K-128KBytes System Diagram ARM Lite Hi-Speed Bus Matrix / Arbiter (max 24MHz) (max 24MHz) Flash I/F Core and operating conditions - ARM Cortex -M DMIPS/MHz up to 24 MHz V to 3.6 V range to +105 C Rich connectivity - 8 communications peripherals Advanced analog - 12-bit1.2 µs conversion time ADC - Dual channel 12-bit DAC Enhanced control - 16-bit motor control timer - 6x 16-bit PWM timers CORTEX TM -M3 CPU 24 MHz JTAG/SW Debug Nested vect IT Ctrl 1 x Systick Timer DMA 7 Channels 1 x 16-bit PWM Synchronized AC Timer Up to 16 Ext. ITs 37/51/80 I/Os 1 x SPI 1 x USART/LIN Smartcard/IrDa Modem Control Bridge ARM Peripheral Bus Bridge 64kB - 128kB Flash Memory 8kB SRAM 20B Backup Data Clock Control ARM Peripheral Bus (max 24MHz) 6 x 16-bit Timer 2 x Watchdog (independent & window) 2-channel 12-bit DAC 1 x 12-bit ADC up to16 channels Temperature Sensor Power Supply Reg 1.8V POR/PDR/PVD XTAL oscillators 32KHz + 4~25MHz Int. RC oscillators 40KHz + 8MHz PLL RTC / AWU 1 x CEC 2 x USART/LIN Smartcard / IrDa Modem Control 1 x SPI 2 x I 2 C

52 On-Chip Buses

53 Why have so many busses? 54 Many designs considerations Master vs Slave Internal vs External Bridged vs Flat Memory vs Peripheral Synchronous vs Asynchronous High-speed vs low-speed Serial vs Parallel Single master vs multi master Single layer vs multi layer Multiplexed A/D vs demultiplexed A/D

54 Advanced Microcontroller Bus Architecture (AMBA) - Advanced High-performance Bus (AHB) Advanced Peripheral Bus (APB) AHB High performance Pipelined operation Burst transfers Multiple bus masters Split transactions APB Low power Latched address/control Simple interface Suitable of many peripherals

55 Example: Cortex M3 Core IF Multiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA BusMatrix added to Harvard architecture allows parallel access Efficient DMA and Rapid data flow Direct path to SRAM through arbiter, guarantees alternating access Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer Increase Peripherals Speed for better performance Dual Advanced Peripheral buses (APB) architecture w/ High Speed APB (APB2) up to 72MHz and Low Speed APB (APB1) up to 36MHz Allows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART, 72MHz PWM Timer, 18MHz toggling I/Os)

56 Details: STM32F100RBT6B

57 Memory RAM (usually SRAM) Volatile memory for runtime execution Fastest access, low amount (<100Kb) Allocates variables Flash ROM On-chip non-volatile memory used for code or data storage 8-512Kb, about 10k write cycles Bootloader: protected section to upload code in flash (Ferroelectric Random Access Memory) FRAM Forefront of next generation non-volatile memory technology On-chip non-volatile memory faster (50ns) and lower power (250x less) than Flash. External memory Connected via serial (I2C, SPI) or dedicated (FSMC) interface 58

58 Memory - Address Space On-Chip FLASH/ROM and RAM memory Everything is mapped into a single, contiguous address space: All memory, including RAM, Flash/ROM, information memory, special function registers (SFRs), and peripheral registers. Flash / ROM RAM Peripherals Memory Address Description Access End: 0FFFFh Interrupt Vector Table Word/Byte Start: 0FFE0h End: 0FFDFh Flash/ROM Word/Byte 0F800h Start *: 01100h End *: 010FFh 0107Fh Information Memory Start: 01000h (Flash devices only) End: 0FFFh Boot Memory Start: 0C00h (Flash devices only) End *: Start: End: Start: End: Start: End: Start: 09FFh 027Fh 0200h 01FFh 0100h 00FFh 0010h 000Fh 0000h RAM 16-bit Peripheral modules 8-bit Peripheral modules Special Function Registers Word/Byte Word/Byte Word/Byte Word Byte Byte 59 59

59 Memory map Statically defined memory map (faster addr decoding) 4GB of address psace

60 General Purpose I/O (GPIO)

61 General Purpose I/O Each MCU pin can be used as a General Purpose digital input or output. Input: read binary value of specified pin, used for simple communication with external world (e.g. button state) Can be configured to trigger interrupt Output: set binary value of specified pin (e.g. LED, simple signal trigger)

62 Each pin is independent GPIO - Inside Inputs/Outputs Ports (out) and Pins (in) are different!!! Output section Input section

63 APB2 GPIO in STM32 The STM32 is well served with general purpose IO pins, having up to 81 bidirectional IO pins with interrupt capability. The IO pins are arranged as five ports each having 16 IO lines. PA [15:0] GPIO port A PB [15:0] PC [15:0] PD [15:0] PE [15:0] GPIO port B GPIO port C GPIO port D GPIO port E

64 GPIO: Block Diagram

65 Avoid floating inputs!!! GPIO General Purpose I/O Use a pull-up/down resistor, GND, or internal programmable logic To Input Logic VCC Button 5.6K Button produces either Vcc or Floating input. Adding a pull-down resistor fixes it. VCC Button 5.6K Some ports have internal programmable resistors Port Pin

66 Let s assume we two possible microcontrollers as in table. A battery of 100mAh a 3.7V. Evaluate the minimal Duty Cycling that maximize the number of tasks executed and achieve 2 weeks for each Microcontroller assuming the minimal time for the active task is 1s at 16MHz and 2s at 8MHz. Active mode Low power mode Exercise MCU A (1.8V to 3V) 2 ma (8Mhz) MCU B (1.5V to 3V) 3 ma (16Mhz) 0.6 ua 1 ua 67 E task = P * time -> MCU-A -> P = 2mA*1.8V ; E task = 3.6mW * 2s = 7.2mJ MCU B-> P = 3mA * 1.5V; E task = 4.5mW * 1s = 4.5mJ E Battery = 100mAh * 3600s * 3.7V-> 1320J Presentation Title

67 Exercise 68 Theoretical Max Numbers tasks (no dissipation in sleep) : E battery / E task MCU A -> MCU B -> Lifetime in Continuous mode[h]: Battery [mah] / Current Consumption [h] MCU A -> 50 h MCU B -> 33 h (But double number of Tasks) Duty Cycling. D = P/T *100. Example MCU A => P = 2s, T = 10s -> D= 20%. Example MCU B=> P = 1s T= 10s -> D= 10% E Sleep = P LowPowerMode * Sleep time [T-Active Time] -> MCU-A -> P = mA*1.8V = 3.6µW * 8s = 8.6µJ MCU B-> P = 0.001mA * 1.5V = 1.5µW * 9s = 13.5µJ Presentation Title

68 Exercise I 69 Evaluate the life time using the following duty cycling MCU B: T= 1000s; P = 1s; D=? MCU A: T = 2000s; P = 2s; D =? Which one last more? How Long? E tot (T) = E sleep (T- P) + E task (T) MCU_B => E task = 4.5mJ ; E sleep = 1.5µW * 999s= 1.498mJ; E tot = 5.99mJ MCU_A => E task = 7.2mJ ; E sleep = 3.6µW * 1998s = 7.19mJ; E tot = 14.49mJ LifeTime (s) = (E battery / E tot ) * T MCU_B => 7 Years! MCU_A => 6 years! Presentation Title