8051 microcontrollers

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1 8051 microcontrollers Presented by: Deepak Kumar Rout Synergy Institute of Engineering and Technology, Dhenkanal Chapter 2

2 Introduction Intel MCS-51 family of microcontrollers consists of various devices and versions. Generally, the MCS-51 family members are also referred to as 8051 microcontrollers. The salient features of 8051 microcontrollers are given below: MCS-51 is a family of 8-bit microcontrollers by Intel, designed around HMOS technology Operating frequency is 12 MHz Available in ROM/EPROM/EEPROM versions. Separate 64K program and 64K data memory. Multiply and Divide instructions available. Has a Boolean processor and supports bitwise operations. Available in CHMOS versions also. 32 I/O lines can be cither used as four 8-bit ports or 32 I/Os 16-bit address bus multiplexed with Port 0 and Port 2. Port 0 is also data bus.

3 MCS-51 Architecture 8051

4 Different blocks of 8051 The various functional blocks of 8051 microcontroller are ALU, control and timing unit, RAM/EPROM/ROM, registers, latches and drivers for ports P0, PI, P2, and P3. Each of these blocks is discussed as follows. ALU Arithmetic and logic unit of 8051 performs arithmetic and logical operation on 8-bit operands. Accumulator is the register, which gets the output of the ALU in most of the arithmetic and logical operations with few exceptions. Apart from addition and subtraction operations, the 8051 hardware also performs multiplication and division operations. Each of the logical operations involves digital gates, AND, OR, NOT, Exclusive OR operations are possible.

5 Boolean Processor There is a separate Boolean Processor integrated within the 8051 microcontroller. It has its own instruction set, accumulator and bit addressable RAM, Carry flag serves as the accumulator. The instructions that allow bit manipulations perform operations like complement bit, set bit, clear bit. There are also conditional branch instructions like jump if bit etc. Logical bitwise AND, OR operations are also supported. The results of these bitwise logical operations are stored into the carry bit, which works as an accumulator. Program and Data Memories There are two separate program and data memories. The code is typically stored in ROM/ EPROM. The program storage is one of the factors that differentiate among the various members of the 8051 family. The program memory of 80C5I is 4K ROM, whereas that of H0C52 is 8K ROM. Another device 87C51 has the program memory 'EPROM' of 4K. Data memory can be internal RAM and off-chip external data RAM. Internal data RAM. for example, in 80C51 is 128 bytes, Some of the internal on-chip RAM locations are also used for controlling the operations of the peripherals such as timers/counters, serial ports, interrupts, etc. called as special function registers (SFRs). Various SFRs can be seen in Fig The external off-chip memory space is accessible in most of the 8051 members. To access the off-chip data RAM, 16-bit address is used. The address (Port 0) and address-data (Port 2) buses hold this address. The lower order byte of the address-data bus is time-multiplexed. Multiplexing reduces the pin count, but it also reduces the speed of the memory access. This is the reason that the external data memory 1 access is always slower as compared to accessing the on-chip RAM. Further, to access the external memory, it is necessary to load the data pointer, which requires one extra instruction.

6 The Oscillator All the 8051 family members use an external crystal for oscillator function. For example, 80C51 operates at 12 MHz frequency. Actually, most of the time, the common frequency is 11,059 MHz because many devices actually run at frequencies below or up to 12 MHz. The slight lower frequency allows one of the timers to generate the clock frequency for the baud rate of 9600 baud for the operation of serial port. It must be noted that only it is necessary to connect the quartz crystal externally and all the other oscillator circuit is on-chip. Timing and Control The whole operation of 8051 microcontroller is synchronous with the clock. Everything happens in step with the clock. Apart from the internal timings, there are control signals ALE, PSEN and RD, WR that are generated by timing and control unit, for accessing the off-chip devices

7 REGISTERS IN MCS-51 There are General-purpose or Working Registers, Stack Pointer, Program Counter and in addition to these CPU registers, there are Special Function Registers (SFRs).

8 General-purpose or Working Registers Accumulator, B-register and four register banks may be used as general purpose registers.

9 Accumulator Similar to any microprocessors like 8085, MCS-51 has an 8-bit accumulator. Accumulator is used by all the arithmetic and logical instructions. Accumulator has a special importance in the sense that, one of the operands is stored in it before the execution of an instruction and it also stores the result after the execution of an instruction. Accumulator of 8051 is also referred to as register 'A. Access to accumulator is faster than access to main memory. Accumulator has direct path to ALU and can immediately store the intermediate result of operation.

10 B-Register B-register is an 8-bit wide register. B-register is available as a general-purpose register when it is not being used by multiplication and division operations. While multiplying, it holds one of the 8-bit operands and after the execution of the multiplication instruction, it stores the higher byte of the result. While dividing, it holds an 8-bit divisor and after the execution of division instruction, the remainder is stored in B-register.

11 Registers RO through R7 These eight registers are used as scratch pad registers. There are four register hanks each containing RO through R7 registers. Each of these registers is 8-bit wide. At a time only one bank can be selected by appropriate setting of bits in the program status word (PSW). These register banks are located in the on-chip RAM. That way, effectively selecting register banks can allow 32 registers to be used while writing programs. Certain instructions can access these registers in RAM directly. Power-up-reset causes bank 0 to be selected by default. Now, if one were writing a byte in R4, it would be stored at RAM location 04H, If in an other case, the programmer is selecting bank 1 and writing a byte in R4, it would store the byte at RAM location OCH. The advantage of this type of access to general-purpose registers is that for programmer it becomes simpler to refer those by register names RO, Rl, etc. Table 2.1 shows the address ranges of the four register banks. Figure 2.3 shows the four register banks located in the on-chip RAM.

12 Four register banks and their location in RAM

13 Stack Pointer and Program Counter Stack Pointer Stack pointer of 805I is 8-bit wide, it is incremented during push or call operations and is decremented during pop or return operation, It may be initialized anywhere in the available on-chip data RAM. After the RESET operation, the stack pointer is initialised to 07H, causing the stack to begin at 08 H. Program Counter (PC) Instruction opcodebytes are fetched from the program memory locations addressed by the program counter. The program counter in 8051 is 16-bit wide, and it can address 64K code bytes. PC always points to the instruction to be fetched and is automatically incremented after fetching the instruction. PC is affected by call and jump instructions. Note that only PC register has no (internal) on-chip RAM address.

14 Special Function Registers (SFR) The 128 bytes of on-chip additional RAM locations from 8OH to OFFH are reserved for the special functions and therefore these are called as Special Function Registers (SFRs). These SFRs are used for control or to show the status of various functions done by 8051 microcontroller. All SFRs are directly addressable and can be read or written to as well. Note that SFR space is only reserved for the special functions and cannot he used for any other purpose. SFRs along with their direct addresses are listed in Table 2.3. Some SFRs are bit addressable and allow their individual bits to be set or cleared by instructions. For example, one can set (or clear) the Port I bit Pl.lusing an instruction SETB P1.0 (or CLR P1.0). The address of Pl.lbit is 91H, Port I has 90H as its byte address, and it is byte addressable too. To change till the 8-bits of Port I in a single stroke, it is required to write (or move) a byte to address 90H. However, there are some SFRs like timer mode control register (TMOD) which is accessible as a byte only.

15 Special Function Registers (SFR)

Program Status Word (PSW) Program status word, or simply PSW, is an 8-bit register. Figure 2.4 shows the PSW register. It consists of carry, auxiliary carry, overflow, and parity flags.

16 Program Status Word (PSW) Program status word, or simply PSW, is an 8-bit register. Figure 2.4 shows the PSW register. It consists of carry, auxiliary carry, overflow, and parity flags. There are bits RSI and RSO for register bank selection, PSW is a bit addressable register. EachofthePSWbitsisreferredas,PSW.X. Thus, PSW.O is the least significant bit (LSB), which is a parity flag, and the most -significant bit (MSB) PSW.7 is the carry flag.

17 PSW Carry Flag (PSW. 7) Carry flag is set when there is a carry out of 7 th bit of result due to certain arithmetic and logical operations. For example, 8-bit addition or subtraction affects carry flag. Auxiliary Carry Flag (PSW. 6) Auxiliary Carry flag (AC) is set when there is a carry out of 3 rd bit, during addition or subtraction operation and otherwise cleared. This is useful in BCD arithmetic F0 (PSW.5) F0 is available to user as a general-purpose flag. This flag can be set/cleared by software, or its status can be observed by software. The user can define its role.

Register Bank Select bits RSI and RSO (PSW.4 and PSW.3, respectively) These are bits for selecting one of the four register banks. Each of these register banks consists of registers RO through R7.

18 Register Bank Select bits RSI and RSO (PSW.4 and PSW.3, respectively) These are bits for selecting one of the four register banks. Each of these register banks consists of registers RO through R7. The register banks are selected as below. As seen earlier, it must be noted that at power-up-reset, bank 0 is selected as a default register bank and both RSI. RSO bits are cleared. Table 2.4 shows the address ranges of four register hanks along with RSI, RSO bits.

19 Overflow Flag (PSW.2) Overflow flag (OV) is set as a result of an arithmetic operation (addition, subtraction, multiplication and division), provided there is a carry out of bit 6, but not out of bit 7 or a carry out of bit 7 but not out of bit 6: otherwise it is cleared. Parity Flag (PSW.0) Parity flag indicates the number of Ts in accumulator. If there are odd number of 'J's in accumulator, then this odd parity will set the parity flag (P) to I. For even parity, the parity flag will be cleared.

20 SFRs Data Pointer(DPTR) DPTR is a 16-bit register consisting of two bytes. The higher byte is referred to as DPI I. whereas the lower byte is referred to as DPL. The data pointer is used for addressing the off-chip dataandcode with the MOVX and MOVC commands, respectively. With 16-hit pointer DPTR, a maximum of 64 K of off-chip data memory and a maximum of 64 K of off-chip program memory can be addressed. It may be used as a general-purpose register also. There is an instruction, "INC DPTR" for incrementing 16-bit contents of DPTR. However, (here is no such insiructign in 8051 to decrement the DPTR. It is also possible to load the DPTR with a 16-bit immediate data using the MOV instruction. Timer Registers Register pairs (TH0, TLO) (TH1, TL1). (TH2. TL2) form 16-bit timer/counter registers 0, 1, 2, respectively. There are instructions for reading and writing these registers byte-wise. Timer/ Counter 2 is only available in The operation may be timing or counting. Further, there are various modes in which timers can be configured. For this purpose there are timer control (TCON) and timer mode registers (TMOD).

21 Ports 0 to 3 P0, PI, P2, P3 are the SFRs corresponding to four I/O ports respectively. Each of these ports is bit addressable as well as byte addressable. I/O ports are covered in detail in the next chapter. Control Registers TCON, TMOD. IE, IP, SCON, PCON contain the control and status for interrupts, serial I/O and timer/counters. Details of these SFRs are discussed in Chapter 6. Capture Registers Register pair (RCAP2H-RCAP2L) are the capture registers for the Timer 2. These are available only in for Timer 2 capture mode operation. In capture mode, a transition at the 8052 T2EX pin causes TH2 and TL2 to be copied into RCAP2H and RCAP2L. Timer 2 also has a 16-bit auto-reload mode and RCAP2H and RCAP2L hold the reload value for this mode.

22 Assignment What makes 8051 an 8-bit microcontroller? Why is a register different from a memory location? Explain. What is an accumulator? Why is it named so? Enlist the various flags in the PSW register. What is the difference between overflow and carry flag?

23 Assignment Discuss the functions of RSO and RSI bits in PSW. Is it possible to write PSW register? Explain with an example the function of AC flag. List the SFRs associated with the following functions: (a) Timer/Counter, (b) interrupts, (c) I/O ports, (d) Serial communication, (e) Power saving modes. Why are the program counter (PC) and data pointer (DPTR) registers of bit wide, whereas the 8051 stack pointer register is 8-bit wide only? Justify.

24 Assignment Discuss the functions of 8051 Boolean processor. Enlist the salient features of 8051 microcontrollers. Compare the features of and stating the need and criteria to select among these family members. Is it true that 8051 microcontroller is a CISC processor? Is it Von Neumann or Harvard architecture? Justify your answer.

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text

e-pg Pathshala Subject : Computer Science Paper: Embedded System Module: 8051 Architecture Module No: CS/ES/5 Quadrant 1 e-text In this lecture the detailed architecture of 8051 controller, register bank,