Migration Guide for Numonyx StrataFlash Wireless Memory (L18/L30) to Numonyx StrataFlash Embedded Memory (P30)

Transcription

1 Migration Guide for Numonyx StrataFlash Wireless Memory (L18/L30) to Numonyx StrataFlash Embedded Memory (P30) Application Note November

2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Numonyx may make changes to specifications and product descriptions at any time, without notice. Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Numonyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries. *Other names and brands may be claimed as the property of others. Copyright 2007, Numonyx B.V., All Rights Reserved. Application Note November

3 Contents 1.0 Introduction Features Comparison Package and Ballouts Lead TSOP Package Ball Easy BGA Package Ball and 79-Ball VF BGA Packages Ball QUAD+ SCSP Hardware Design Considerations AC Read Specifications AC Write Specifications DC Voltage Characteristics Power and Voltage Regulation Program/ Erase Voltages Software Design Considerations Device Identification Blocking Architecture Status Register Synchronous Read Mode Differences Program/Erase Operations Program/Erase Characteristics Design Tools Numonyx Flash Software A Additional Information November 2007 Application Note

4 Revision History Date of Revision Revision Description August Original version April Removed references to 1-Gbit and updated format for new branding. November Applied Numonyx branding. Application Note November

5 1.0 Introduction This application note describes migrating from the Numonyx StrataFlash Wireless Memory (L18/L30) called hereafter the L18/L30 Wireless Memory to the Numonyx StrataFlash Embedded Memory (P30) called hereafter the P30 Embedded Memory. This document was written based on device information available at the time. Any changes in specifications to either device might not be reflected in this document. Refer to the appropriate documents or sales personnel for the most current product information before finalizing any design. 2.0 Features Comparison Table 1 compares the various features and specifications of the L18/L30 Wireless Memory and the P30 Embedded Memory. Table 1: Device Comparison, L18/L30 Wireless Memory and P30 Embedded Memory (Sheet 1 of 2) Feature L18/L30 Wireless Memory Specification P30 Embedded Memory Note Process Lithography 130 nm 130 nm Device Densities 64Mb, 128Mb, 256Mb 64Mb, 128Mb, 256Mb, 512Mb Packages VF BGA, QUAD+ SCSP TSOP, Easy BGA, QUAD+ SCSP Block Architecture Operating Voltage Range Performance Security Blocking Asymmetrical Asymmetrical Main Blocks 128-KByte 128-KByte Parameter Blocks 4 x 32-KByte, top or bottom 4 x 32-KByte, top or bottom V CC (core) 1.7 V 2.0 V 1.7 V 2.0 V V CCQ (I/O) V PP Asynchronous Initial Read Access (t AVQV ) Asynchronous Page Access (t APA ) 1.7 V V (L18) 1.35 V V (L18 Extended I/O) 1.7 V 3.6 V 2.2 V V (L30) 0.9 V V (L18) 0.9 V V (L30) V PPL = 1.7 V 3.6 V V PPH = 8.5 V 9.5 V V PPH = 8.5 V 9.5 V 1 85 ns (L18/L30) 90 ns (L18 Extended I/O) 85 ns 25 ns (4 word) 25 ns (4 word) Program Suspend (typ/ max) 20/ 25 µs 20/ 25 µs Erase Suspend (typ/ max) 20/ 25 µs 20/ 25 µs Synchronous Read Support 54 MHz, t CHQV = 14 ns (L18) 40 MHz, t CHQV = 20 ns 52 MHz, t CHQV = 17 ns (L30) 52 MHz, t CHQV = 17 ns OTP Registers 128 bits bits 128 bits bits Block Locking Volatile, defaults to locked after each power cycle Volatile, defaults to locked after each power cycle Lockdown Yes Yes OTP Block Locking No Yes, 4 parameter blocks and 3 main array blocks 2 November 2007 Application Note Order Number:

6 Table 1: Device Comparison, L18/L30 Wireless Memory and P30 Embedded Memory (Sheet 2 of 2) Feature L18/L30 Wireless Memory Specification P30 Embedded Memory Note Program Program Buffer Size 32 Word 32 Word Write Protection Yes, V PP = 0 Yes, V PP = 0 Erase Cycles 100, ,000 Temperature Operating Temperature 25 C to +85 C 512-Mbit devices and below: 40 C to +85 C I/O Bus Bus Width x16 only x16 only Note: 1. In typical operation, the VPP program voltage is V PPL. VPP can be connected to 9 V for a maximum of 80 hours MHz, t CHQV = 17 ns is line item per request. 3.0 Package and Ballouts Lead TSOP Package Available for the P30 Embedded Memory. Refer to the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet for details Ball Easy BGA Package Available for the P30 Embedded Memory. Refer to the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet for details Ball and 79-Ball VF BGA Packages Available for the L18/L30 Wireless Memory. Refer to the latest Numonyx StrataFlash Wireless Memory (L18/L30) Datasheet for details Ball QUAD+ SCSP The P30 Embedded Memory and the L18/L30 Wireless Memory have the same basic ballout in SCSP package, referred to as QUAD+ ballout as shown in Figure 1 on page 7. For the 512Mb density, the P30 Embedded Memory and the L18/L30 Wireless Memory have a difference designers must be aware of. As the 512Mb P30 Embedded Memory is a 2-die stacked device, this implements virtual chip select logic, which allows a 512Mb P30 hardware device look monolithic to the CPU and system (1 CE#). The L18/ L30 Wireless Memory has a 256Mb/256Mb stacked device, having either a virtual chip select logic (1 CE#) lead-free only version and a 2 CE# version (1 CE# for each 256Mb L18/L30 die in a SCSP). Table 2: QUAD+ SCSP Chip Select Logic Selected Flash Die# 256/256 1CE# L18/L30 Wireless Memory 256/256 2CE# L18/L30 Wireless Memory 512Mb P30 Embedded Memory Die#1 F1-CE# + A24=V IL F1-CE# (A24 not used) F1-CE# + A24=V IL Die#2 F1-CE# + A24=V IH F2-CE# (A24 not used) F1-CE# + A24=V IH Application Note November Order Number:

7 The 512Mb P30 Embedded Memory can drop into a 256/256 L18/L30 2CE# socket if the processor has an A24 address bit, or a GPIO that can be used to control the A24 signal of the P30 device. Otherwise, Figure 2, Enabling Recommendation, 256/256 L18/L30 2CE# and 512Mb P30 in Address-Constraint System on page 8 and Table 3, Component Application Table for Address Constraint System on page 8 show a recommended solution enabling 512Mb P30 Embedded Memory and a 256/256 L18/ L30 2CE# device in the same socket on an address-constraint system. Figure 1: P30 Embedded Memory, 88-Ball QUAD+ SCSP Ballout Pin A DU DU Depop Depop Depop Depop DU DU A B A4 A18 A19 VSS VCC VCC A21 A11 B C A5 RFU A23 VSS RFU CLK A22 A12 C D A3 A17 A24 VPP RFU RFU A9 A13 D E A2 A7 RFU WP# ADV# A20 A10 A15 E F A1 A6 RFU RST# WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H RFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J RFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# RFU RFU RFU RFU VCC VCCQ RFU K L VSS VSS VCCQ VCC VSS VSS VSS VSS L M DU DU Depop Depop Depop Depop DU DU M Notes: 1. A0 is the least significant address bit. 2. A22 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC). 3. A23 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC). 4. A24 is valid for 512-Mbit P30 and 256/256 L18/L30 1CE# only; otherwise, it is a no connect (NC). November 2007 Application Note Order Number:

8 Figure 2: Enabling Recommendation, 256/256 L18/L30 2CE# and 512Mb P30 in Address- Constraint System Processor CS0# CS1# U1 R3 0 ohm R1 0 ohm R2 0 ohm P30 or L18/L30 Flash Memory A24 CE1# CE2# Note: Consider the propagation delay of the AND gate (U1) affecting A24 and CE# signals, for bus operation and timings and when setting the processor registers. Table 3: Component Application Table for Address Constraint System 256/256 L18/L30 2 CE 512 Mbit P30 U1 (AND Gate) Depopulated Populated R1 Depopulated Populated R2 Populated Depopulated R3 Populated Depopulated 4.0 Hardware Design Considerations 4.1 AC Read Specifications Refer to the latest Numonyx StrataFlash Wireless Memory (L18/L30) Datasheet and the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet when comparing read timing specifications. 4.2 AC Write Specifications Refer to the latest Numonyx StrataFlash Wireless Memory (L18/L30) Datasheet and the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet when comparing write timing specifications. 4.3 DC Voltage Characteristics The P30 Embedded Memory has a wide I/O range for multiple applications using CMOS and TTL. The P30 Embedded Memory has the same DC Voltage specs as with L18/L30 Wireless Memory using CMOS inputs. For details, refer to the latest Numonyx StrataFlash Wireless Memory (L18/L30) Datasheet and the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet. Application Note November Order Number:

9 4.4 Power and Voltage Regulation Both the P30 Embedded Memory and L18/L30 Wireless Memory incorporate technology that enables low power designs. Both the P30 Embedded Memory and L18/L30 Wireless Memory support read, program, and erase operations at 1.8 V V CC. Active read current of the P30 Embedded Memory during asynchronous single-word read, page read mode, and 40MHz burst read mode are the same as with L30 device, with L18 device having slightly lower specs than P30. Program and erase currents of the P30 Embedded Memory are the same as with L30 device, with L18 device having slightly lower specs than P30. System designers should also consider the following: Standby current levels (Iccs) Transient voltage/current peaks produced by falling and rising edges of CE# and OE# For more details, refer to the latest Numonyx StrataFlash Wireless Memory (L18/ L30) Datasheet and the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet. 4.5 Program/ Erase Voltages When programming or erasing flash memory, a valid V PP voltage must be present on VPP. In addition to programming and erasing at 1.8 V, both the P30 Embedded Memory and L18/L30 Wireless Memory support factory and buffered programming modes. Both P30 Embedded Memory and L18/L30 Wireless Memory can use a V PP range of 8.5 V to 9.5 V, providing faster program/erase performance and improve factory throughput. 5.0 Software Design Considerations 5.1 Device Identification As with all Numonyx flash memory devices, the P30 Embedded Memory has its own unique device identification code. To pre-enable system software for the P30 Embedded Memory, insert conditional jumps to device-specific configuration routines, based on the device ID code that is read during system initialization. Table 4 shows the device IDs for the P30 Embedded Memory, L18 and L30 Wireless Memory devices. Table 4: Device ID codes - P30 Embedded Memory Device Identifier Codes ID Type Device Address 1 Device Density L18 Wireless Memory L30 Wireless Memory P30 Embedded Memory -T: Top Paramete -B: Bottom Parameter -T: Top Parameter -B: Bottom Parameter -T: Top Parameter -B: Bottom Parameter Manufacturer Code 0x00 All 0089 Device Code 0x01 64-Mbit 880B 880E A 128-Mbit 880C 880F B 256-Mbit 880D C Note: Numonyx reserves other locations within the Identifier address space for future use. November 2007 Application Note Order Number:

10 As the 512Mb P30 devices are multiple-die stacked devices, reading their device IDs would be the same as with L18/L30 Wireless Memory multiple-die stack device, which is referencing the specific device ID of the particular flash memory die inside the stack device. 5.2 Blocking Architecture The P30 Embedded Memory has the same block sizes (four 32-KB parameter blocks, 128-KB Main Blocks) and blocking architecture as with L18/L30 Wireless Memory. The P30 Embedded Memory is also segmented into multiple Programming Regions while the L18/L30 Wireless Memory is segmented into multiple partitions. Only designers doing XIP (Execute In Place) applications should take this into consideration. For details, refer to the latest Numonyx StrataFlash Wireless Memory (L18/L30) Datasheet and the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet. 5.3 Status Register Reading the status register of the P30 Embedded Memory is the same as with L18/L30 Wireless Memory. The status register bits definition are the same, except for the SR[0] bit. SR[0] bit in P30 Embedded Memory is defined as BEFP Status bit, while for the L18/ L30 Wireless Memory it is defined as the Partition Status bit. For details, refer to the latest Numonyx StrataFlash Wireless Memory (L18/L30) Datasheet and the latest Numonyx StrataFlash Embedded Memory (P30) Datasheet. 5.4 Synchronous Read Mode Differences The P30 Embedded Memory has the same Read Configuration Register (RCR) definition and set-up procedure as with L18/L30 Wireless Memory. For burst read mode, latency count in the RCR may need to be adjusted accordingly when migrating from L18/L30 to P30 as L18/L30 and P30 have different maximum burst read speeds. 5.5 Program/Erase Operations Both the P30 Embedded Memory and the L18/L30 Wireless Memory offer factory program and erase voltage range (V PPH ) to enhance their respective performances. The factory programming voltage can be used for Single Word, Buffered Programming, and Buffer Enhanced Factory Programming (BEFP). Refer to Table 5, Programming Voltage Comparison, L18/L30 Wireless Memory and P30 Embedded Memory. Table 5: Programming Voltage Comparison, L18/L30 Wireless Memory and P30 Embedded Memory Symbol Parameter L18/L30 Wireless Memory P30 Embedded Memory Unit Notes Min Nom Max Min Nom Max T C Operating Temperature C 1 V PPL V PP Voltage Supply (Logic Level) L L V V PPH Factory Programming V PP Note: 1. For the P30 Embedded Memory, 512-Mbit devices and below are 40 C to +85 C. Application Note November Order Number:

11 5.6 Program/Erase Characteristics The P30 Embedded Memory has the same program and erase characteristics as with the L18/L30 Wireless Memory, except for maximum single-word program time (W200). Table 6 shows the program and erase characteristics difference between the P30 Embedded Memory and the L18/L30 Wireless Memory. Table 6: Program and Erase Characteristics - P30 Embedded Memory Number Symbol Parameter L18/L30 Wireless Memory P30 Embedded Memory Units Notes Min Typ Max Min Typ Max W200 t PROG/W Single-Word Program Time V PPL V PPH µs 1 Notes: 1. Typical values measured at T C = +25 C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system overhead. Sampled, but not 100% tested. 2. Averaged over entire device. 6.0 Design Tools Design tools for the P30 Embedded Memory include VHDL and Verilog bus functional models, as well as IBIS files. These tools are available on the Numonyx website, or contact an Numonyx field representative to obtain them. 6.1 Numonyx Flash Software Numonyx offers a variety of software solutions for its flash memory products. The following sections describe the available flash software Numonyx Flash Data Integrator Numonyx Flash Data Integrator software (called hereafter Numonyx FDI software) is an Numonyx-supported code, data, and file manager for use in real-time embedded applications. The Data Manager component of the Numonyx FDI software provides a storage API (application programmer interface) to replace EEPROM with flash memory. The Data Manager also includes a high-performance interface for streaming data in voice recording and multimedia applications, as well as packetized data. The Code Manager component of the Numonyx FDI software allows for direct execution of code, including Java* applets and native CPU software. The FDI File Manager component presents a user-friendly ANSI-style interface for software developers, streamlining the development of data-centric applications. Numonyx FDI software is founded upon robust power-loss recovery mechanisms to reduce data corruption, even through fluctuations and failure of power to the system. In addition, the intelligent wear-leveling techniques of Numonyx FDI increase cycling endurance of flash memory blocks. Numonyx FDI software comprehends the available features of available flash memory. When an internal data buffer is present (such as with the P30 Embedded Memory), Numonyx FDI optimizes write performance by storing data through the internal data buffer. November 2007 Application Note Order Number:

12 Numonyx FDI software also provides an interface for storing information in multiple User Protection Registers, or extended One-Time Programmable (OTP) bits. Numonyx FDI software also supports page and synchronous burst modes available in many flash memory devices Numonyx Flash Persistent Storage Manager Numonyx Persistent Storage Manager software (called hereafter Numonyx PSM software) simplifies designs by combining all non-volatile memory functions into a single chip. Numonyx PSM software works in conjunction with the file system in Microsoft Windows CE* Operating System (OS) to provide simultaneous access to separate code and file partitions in the same chip. Unlike other data-only storage solutions, the code can be directly executed, demand paged, or memory mapped. This allows a designer to effectively trade-off between performance, power, and cost in a design. Numonyx PSM software is designed to optimize benefits of Numonyx StrataFlash memory, which employs two-bit-per-cell storage technology to deliver reliable, costeffective, high density memory for designs using the Microsoft Windows CE* Operating System Numonyx Virtual Small Block File Manager Numonyx Virtual Small Block File Manager (called hereafter Numonyx VFM) is an Numonyx provided reference code which provides for disk-like sector and file access to the Numonyx Flash memory and accommodates handling code and data in same component. Numonyx VFM is recommended for the Linux based system. The VSB Flash media manager component of the Numonyx VFM package handles flash read/write/erase, wear leveling and sector management. The Numonyx VFM component of the Numonyx VFM package handles the general file manager functions, including (but not limited to) File Write, File Erase, File Delete, File Seek, Tell, Reclaim, Power Loss Recovery and media Cleanup. Numonyx VFM works as a file manager or can be adapted to operate under an existing file system or operating system through the high level API. Numonyx VFM has a High performance edit capability. Numonyx VFM package has a small code size (14K to 20K, 2K to 8K RAM). It allows the creation of virtual small blocks sectors in the larger flash erase blocks. Other features supported are Multiple partitions, concurrent opening of several files per partition, flat directory structure with no subdirectories and many more. Appendix A Additional Information Order/Document Number Document/Tool Numonyx StrataFlash Embedded Memory (P30) Datasheet Numonyx StrataFlash Wireless Memory (L18) Datasheet Numonyx StrataFlash Wireless Memory (L30) Datasheet Numonyx Flash Data Integrator (FDI) User s Guide Numonyx Persistent Storage Manager User Guide Application Note November Order Number:

13 Order/Document Number Document/Tool Numonyx Flash Memory Chip Scale Package User s Guide AP-782 Numonyx Flash Memory Design for a Stacked Chip Scale Package (SCSP) Note: Contact your local Numonyx or distribution sales office or visit Numonyx s World Wide Web home page at for technical documentation, tools, and the most current information on Numonyx Flash Memory. November 2007 Application Note Order Number:

14 Application Note November Order Number: