SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR

Size: px
Start display at page:

Download "SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR"

Transcription

1 SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN ( ) Course / Branch : B.Sc CS Total Hours : 50 Subject Name : Digital Electronics & Subject Code : SAE2B Microprocessors Faculty Name : M.Sudharasan /D.Buvaneshwari Designation : Asst.Pressor Semester / Year : EVEN / I : 5 PPT Hours : Minimum Hour per Unit Aim: To make the students understand the Number Systems, Components and working Digital Computer and Microprocessor. Objectives: To describe basic terminology about Digital Computer. Explain various Logic Gates. Describe Flip Flops and Registers. To learn various Number Systems. Text Book(s):. M. Morris Mano, 2005, Digital Logic and Computer Design, Prentice-Hall India Pvt. Ltd. 2. Ramesh S. Gaonkar, 999, Microprocessor Architecture, Programming, and Applications with the 8085, 5 th Edition, Penram International Publishing (India) Pvt. Ltd. Book(s):. D. P. Leach and A. P. Malvino, 2002, Digital Principles and Applications, 5th Edition, Tata McGraw, Hill Publishing Co. Ltd. 2. V. Vijayendran, 2004, Digital Fundamentals, S. Viswanathan (Printers & Publishers) Pvt. Ltd. 3. V. Vijayendran, 2004, Fundamentals Microprocessor 8085, S. Viswanathan (Printers & Publishers) Pvt. Ltd. 4. N. K. Srinath, 2005, 8085 Microprocessor Programming and Interfacing, Prentice-Hall India Pvt. Ltd. Website Link:

2 Page Nos Sl. Unit Topic(s) Unit-I: Binary Systems & Code conversion,boolean Algebra & Logic Gates Truth Tables Universal Gates Simplification Boolean functions: SOP, POS methods K-map, Combinational Logic: Adders & Subtractors Multiplexer Demultiplexer - Encoder Decoder.. I 2. I i. Binary Systems a. Digital Computers & Systems b. Binary Numbers ii. Code Conversion a. Number Base Conversion b. Complements 3. c. Binary Storage and d. Registers, Binary Logic Boolean Algebra 4. I a. Basic Definitions b. Axiomatic Definitions and Theorems 5. c. Canonical and Standard 6. Forms i. Logic Gates a. Digital Logic Gates b. IC Logic Families 7. I i. Truth Tables ii. Universal Gates Simplification Boolean Fuctions 8. I a. Sum Products (SOP) b. Product Sums (POS) 9. I 0 I. I 2. I 3. I K Map K Map a. Two and Three Variable Maps a. Four Variable Maps K Map a. Five and Six Variable Maps Combinational Logic a. Adders and Subractors b. Multiplexers c. Combinational Logic a. Demultiplexers b. Encoders and Decoders 4. Unit Test I T -6 T 9-0 T -30 T T T T T T T T T 6-23 T

3 Page Nos Sl. Unit Topic(s) Unit-II: Sequential Logic: RS, Clocked RS, D, JK, Master Slave JK, T Flip-Flops Shift Registers Types Shift Registers Counters: Ripple Counter Synchronous Counters Up-Down Counter. 5. II 6. II Sequential Logic a. Flip Flops b. RS Flip Flop c. Clocked RS Flip Flop T Flip Flops a. D Flip Flop T b. JK Flip Flop T II 9. II Flip Flops a. Master Slave JK Flip Flop T b. T Flip Flops Shift Registers a. Introduction Registers T II b. Introduction to Shift Registers T II 22. II 23. II 24. II Shift Registers a. Types Registers Counters a. Introduction to Counters b. Ripple Counters Synchronous Counters a. Introduction to Synchronous Counters b. Types Synchronous Counters Synchronous Counters a. Timing Sequences b. Up-Down Counters 25. Unit Test II T T T T

4 Sl. Unit Topic(s) Page Nos Unit-III: Introduction to microprocessor Microprocessor and assembly languages- microprocessor architecture and its operation Memory-I/O Devices-8085 MPU introduction to instructions- data transfer operations-addressing modes-. Arithmetic, Logic and branch operations- Writing assembly level programs. 26 III Introduction to microprocessor a. Microprocessor b. Organization a microprocessor based system c. Computer language d. Machine language III e. Assembly language f. ASCII code g. High level language h. Operating systems i. Large,Medium size, microcomputers III Microprocessor and assembly languages a. The 8085 programming model 3-34 b. Instruction classification c. Instruction data format and 30 III storage d. Overview the 8085 instruction set e. Writing and hand assembling a program microprocessor architecture and its operation a. Microprocessor-initiated 3 III operations, 8085 bus organization b. Internal data operations,8085 registers c. Pheripheral or externally initiated operations 32 III Memory and I/O 33 III 8085 MPU a micrprocessor b. Microprocessor communication and bus timings c. Demultiplexing the bus AD7- AD0 d. Generating control signals

5 e. Decoding and executing an instruction. 34 III Data transfer operations Addressing modes 35 III Arithmetic Logic and branch operations Writing assembly level programs 36 III Unit Test- III Unit-IV: Time Delay Programs: Time Delay Using One Register Using a Register Pair Using a Loop within Loop Technique Counter Design with Time Delay Stack and Subroutines BCD to Binary Conversion and Vice-versa BCD to HEX Conversion and Vice-versa Binary to ASCII Conversion and Vice-versa BCD Addition and Subtraction. 38 IV Time delay programs:time delay using one register- 39 IV Using a register pair IV Using a loop within loop technique IV Counter design with time delay IV Stack and subroutines IV 44 IV BCD to binary conversion and vice versa Binary to ASCII Conversion and Vice-versa BCD Addition and Subtraction Unit Test IV Sl. Unit Topic(s) Page Nos Unit-V: 8085 Interrupt Vectored Interrupts Interfacing I/O Devices: Basic Interfacing Concepts Interfacing Input Devices- Memory-Mapped I/O. 46 V 8085 Interrupt V Vectored Interrupts

6 Sl. Unit Topic(s) Page Nos 48 V Interfacing I/O Devices: Basic Interfacing Concepts a. Memory interfaces RAM b. Memory interfaces ROM R V 50 V Interfacing I/O Devices a. Interfacing Input Devices b. Interfacing output Devices Memory-Mapped I/O. R R Unit Test- V * T Text Book / R Book 6

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan

UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UPY14602-DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I - NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal- Binary- Octal- Hexadecimal number systems-inter conversions-bcd code- Excess

More information

INTRODUCTION OF MICROPROCESSOR& INTERFACING DEVICES Introduction to Microprocessor Evolutions of Microprocessor

INTRODUCTION OF MICROPROCESSOR& INTERFACING DEVICES Introduction to Microprocessor Evolutions of Microprocessor Course Title Course Code MICROPROCESSOR & ASSEMBLY LANGUAGE PROGRAMMING DEC415 Lecture : Practical: 2 Course Credit Tutorial : 0 Total : 5 Course Learning Outcomes At end of the course, students will be

More information

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN

SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.2017-18 INSTRUCTOR: Sri A.M.K.KANNA

More information

DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.

DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER. DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development

More information

SCHEME OF EXAMINATION FOR B.Sc.(COMPUTER SCIENCE) SEMESTER SYSTEM (Regular Course) w.e.f Scheme for B.Sc.-I. Semester-I. Internal Assessment

SCHEME OF EXAMINATION FOR B.Sc.(COMPUTER SCIENCE) SEMESTER SYSTEM (Regular Course) w.e.f Scheme for B.Sc.-I. Semester-I. Internal Assessment SCHEME OF EXAMINATION FOR B.Sc.(COMPUTER SCIENCE) SEMESTER SYSTEM (Regular Course) w.e.f. 2013-14 Scheme for B.Sc.-I Sr. No. Paper 1 Paper-I Computer And Programming Fundamentals Semester-I Internal Assessment

More information

Semester: I Credits: 5. Category: MC No.of hrs/week: 5 CA PROGRAMMING IN C

Semester: I Credits: 5. Category: MC No.of hrs/week: 5 CA PROGRAMMING IN C Semester: I Credits: 5 Category: MC No.of hrs/week: 5 CA1505 - PROGRAMMING IN C Objective: This course aims at explaining the basic concepts of computers and an easy understanding of C Language by the

More information

TEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I

TEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. Part-I TEACHING & EXAMINATION SCHEME For the Examination -2015 COMPUTER SCIENCE THEORY B.Sc. Part-I CS.101 Paper I Computer Oriented Numerical Methods and FORTRAN Pd/W Exam. Max. (45mts.) Hours Marks 150 2 3

More information

Digital logic fundamentals. Question Bank. Unit I

Digital logic fundamentals. Question Bank. Unit I Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative

More information

B.Sc II Year Computer Science (Optional)

B.Sc II Year Computer Science (Optional) Swami Ramanand Teerth Marathwad University, Nanded B.Sc II Year Computer Science (Optional) (Semester Pattern) ( W.E.F. June 2010) Paper No VI VII Paper Title Digital Electronics & 8085 Microprocessor

More information

R10. II B. Tech I Semester, Supplementary Examinations, May

R10. II B. Tech I Semester, Supplementary Examinations, May SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31

More information

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT

KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:00-11:50AM Class

More information

SEMESTER SYSTEM, A. PROPOSED SCHEME FOR B.Sc. (ELECTRONICS MAINTENANCE)

SEMESTER SYSTEM, A. PROPOSED SCHEME FOR B.Sc. (ELECTRONICS MAINTENANCE) SEMESTER SYSTEM, 2010-2013 A PROPOSED SCHEME FOR B.Sc. (ELECTRONICS MAINTENANCE) CLASS/ SEMESTER Sem-III Sem-IV B. Sc (Elex. Maint) EL-2101 Op-Amp & its Applications EL-2102 Digital Electronics II EL-2103

More information

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN

B.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don

More information

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment

HANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)

More information

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.

II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit. Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic

More information

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351-DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation

More information

(ii) Simplify and implement the following SOP function using NOR gates:

(ii) Simplify and implement the following SOP function using NOR gates: DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be

More information

VALLIAMMAI ENGINEERING COLLEGE

VALLIAMMAI ENGINEERING COLLEGE VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201- DIGITAL PRINCIPLE AND SYSTEM DESIGN

More information

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)

CONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...

More information

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS

VALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 2015-2016 (ODD

More information

Hours / 100 Marks Seat No.

Hours / 100 Marks Seat No. 17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)

More information

END-TERM EXAMINATION

END-TERM EXAMINATION (Please Write your Exam Roll No. immediately) END-TERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA-103 Subject: Digital Electronics Time: 3 Hours Maximum

More information

PGDCA SEMESTER-I PGDCA 101: PC SOFTWARE: Unit-1: Introduction

PGDCA SEMESTER-I PGDCA 101: PC SOFTWARE: Unit-1: Introduction PGDCA SEMESTER-I PGDCA 101: PC SOFTWARE: - Introduction to personal computer Concept of hardware & software, program, data processing, classification of PC software, Computer Applications. - Overview of

More information

Injntu.com Injntu.com Injntu.com R16

Injntu.com Injntu.com Injntu.com R16 1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by K-map? Name it advantages and disadvantages. (3M) c) Distinguish between a half-adder

More information

Scheme G. Sample Test Paper-I

Scheme G. Sample Test Paper-I Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable

More information

R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April

R07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April SET - 1 II B. Tech II Semester, Supplementary Examinations, April - 2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions

More information

UNIVERSITY POLYTECHNIC B.I.T., MESRA, RANCHI. COURSE STRUCTURE (W.E.F Batch Students) (Total Unit 7.5) Sessional Unit Code. Theory Unit Course

UNIVERSITY POLYTECHNIC B.I.T., MESRA, RANCHI. COURSE STRUCTURE (W.E.F Batch Students) (Total Unit 7.5) Sessional Unit Code. Theory Unit Course COURSE STRUCTURE (W.E.F. 2011 Batch Students) (Total Unit 7.5) Course Theory Unit Course Sessional Unit Code Code DCP 4001 Data Structures 1.0 DCP 4002 Data Structures Lab. 0.5 DEC 4003 Electronics Circuits

More information

www.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012--DIGITAL

More information

Computer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Computer Architecture: Part III. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Computer Architecture: Part III First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Decoders Multiplexers Registers Shift Registers Binary Counters Memory

More information

Computer Organization

Computer Organization A Text Book of Computer Organization and Architecture Prof. JATINDER SINGH Director, GGI, Dhaliwal Er. AMARDEEP SINGH M.Tech (IT) AP&HOD, Deptt.of CSE, SVIET, Banur Er. GURJEET SINGH M.Tech (CSE) Head,

More information

SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI

SHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL

More information

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.

Principles of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system. Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

Philadelphia University Student Name: Student Number:

Philadelphia University Student Name: Student Number: Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019

More information

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) UNIT-I

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) UNIT-I SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : CO (16MC802) Year & Sem: I-MCA & I-Sem Course & Branch: MCA Regulation:

More information

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni

NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni-625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering

More information

SRM UNIVERSITY FACULTY OF SCIENCE AND HUMANITIES DEPARTMENT OF PHYSICS AND NANOTECHNOLOGY COURSE PLAN FOR PHY0408

SRM UNIVERSITY FACULTY OF SCIENCE AND HUMANITIES DEPARTMENT OF PHYSICS AND NANOTECHNOLOGY COURSE PLAN FOR PHY0408 SRM UNIVERSITY FACULTY OF SCIENCE AND HUMANITIES DEPARTMENT OF PHYSICS AND NANOTECHNOLOGY COURSE PLAN FOR PHY0408 Course Code : PHY0408 Course Title : MICROPROCESSORS AND MICROCONTROLLERS Semester : II

More information

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I

COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA

More information

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method

R a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method SET - 1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove de-morgan laws c) Implement two input EX-OR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What

More information

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3

SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3 UNIT - I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented

More information

Syllabus for Bachelor of Technology. Computer Engineering. Subject Code: 01CE0501. Subject Name: Microprocessor Fundamentals & Programming

Syllabus for Bachelor of Technology. Computer Engineering. Subject Code: 01CE0501. Subject Name: Microprocessor Fundamentals & Programming Subject Code: 01CE0501 Subject Name: Microprocessor Fundamentals & Programming B.Tech. Year - III Objective: The objective of the course is to expose to the students to the architecture and instruction

More information

SEMESTER SYSTEM, PROPOSED SCHEME FOR B.Sc. (ELECTRONICS), B.Sc. (ELECTRONICS MAINTENANCE)

SEMESTER SYSTEM, PROPOSED SCHEME FOR B.Sc. (ELECTRONICS), B.Sc. (ELECTRONICS MAINTENANCE) SEMESTER SYSTEM, 2008 PROPOSED SCHEME FOR B.Sc. (ELECTRONICS), B.Sc. (ELECTRONICS MAINTENANCE) CLASS/ SEMESTER Sem-III Hons.-> Sem-IV Hons.-> B. Sc (Elex) B. Sc (Elex. Maint) EL-2101 Op-Amp & its Application

More information

Course Description: This course includes concepts of instruction set architecture,

Course Description: This course includes concepts of instruction set architecture, Computer Architecture Course Title: Computer Architecture Full Marks: 60+ 20+20 Course No: CSC208 Pass Marks: 24+8+8 Nature of the Course: Theory + Lab Credit Hrs: 3 Course Description: This course includes

More information

QUESTION BANK FOR TEST

QUESTION BANK FOR TEST CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice

More information

COURSE DESCRIPTION. CS 232 Course Title Computer Organization. Course Coordinators

COURSE DESCRIPTION. CS 232 Course Title Computer Organization. Course Coordinators COURSE DESCRIPTION Dept., Number Semester hours CS 232 Course Title Computer Organization 4 Course Coordinators Badii, Joseph, Nemes 2004-2006 Catalog Description Comparative study of the organization

More information

Semester I.

Semester I. Semester I Code No. Name of the Paper Marks (Theory + CCE) FC Hindi 35+15 FC English 35+15 FC Development of Entrepreneurship 35+15 FC Udiyamita vikas 35+15 BCA 101 Computer Fundamentals 35+15 BCA 102

More information

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)

SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE) SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: II-B.Tech & I-Sem Course & Branch: B.Tech

More information

Course Title III Allied Practical** IV Environmental Studies #

Course Title III Allied Practical** IV Environmental Studies # Part Ins. hrs / week Dur.Hr s. CIA Marks Total Marks Credit Page 1 of 5 BHARATHIAR UNIVERSITY,COIMBATORE-641 046 B.Sc. PHYSICS DEGREE COURSE SCHEME OF EXAMINATIONS (CBCS PATTERN) (For the students admitted

More information

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS

KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL

More information

UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS)

UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PART-A (2 MARKS) SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.

More information

DE Solution Set QP Code : 00904

DE Solution Set QP Code : 00904 DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and

More information

CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES.

CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. CS6201-DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PART-B UNIT-I BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all

More information

DIGITAL ELECTRONICS. P41l 3 HOURS

DIGITAL ELECTRONICS. P41l 3 HOURS UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER

More information

Hours / 100 Marks Seat No.

Hours / 100 Marks Seat No. 17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,

More information

Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore

Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. Radhakrishnan Professor of Computer Science

More information

B.Sc- ELECTRONICS-SYLLABUS SEMESTER: V PAPER V - MICROPROCESSORS (INTEL 8085) (60 OURS) Work load:60 hrs per semester

B.Sc- ELECTRONICS-SYLLABUS SEMESTER: V PAPER V - MICROPROCESSORS (INTEL 8085) (60 OURS) Work load:60 hrs per semester ADIKAVI NANNAYA UNIVERSITY, RAJAMAHENDRAVARAM B.Sc- ELECTRONICS-SYLLABUS SEMESTER: V PAPER V - MICROPROCESSORS (INTEL 8085) (60 OURS) Wk load:60 hrs per semester 4 hrs/week UNIT- I (12 hrs) ARCHITECTURE

More information

Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru

Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru Government of Karnataka Department of Technical Education Board of Technical Examinations, Bengaluru Course Title: DIGITAL ELECTRONICS Course Code : 15EE34T Semester : III Course Group : Core Teaching

More information

LOGIC DESIGN. Dr. Mahmoud Abo_elfetouh

LOGIC DESIGN. Dr. Mahmoud Abo_elfetouh LOGIC DESIGN Dr. Mahmoud Abo_elfetouh Course objectives This course provides you with a basic understanding of what digital devices are, how they operate, and how they can be designed to perform useful

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS

BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES

More information

DIGITAL ELECTRONICS. Vayu Education of India

DIGITAL ELECTRONICS. Vayu Education of India DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education

More information

Problem solving using standard programming techniques and Turbo C compiler.

Problem solving using standard programming techniques and Turbo C compiler. Course Outcome First Year of B.Sc. IT Program Semester I Course Number:USIT 101 Course Name: Imperative Programming Introduces programming principles and fundamentals of programming. The ability to write

More information

MULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR

MULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEW-E-F 1/13 18 FEBRUARY

More information

This tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.

This tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture. About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional

More information

SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR

SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207-208) Course / Branch : M.Sc CST Total Hours : 50 Subject Name : Computer Architecture

More information

PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).

PART B. 3. Minimize the following function using K-map and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10). II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (Part-A

More information

D I G I T A L C I R C U I T S E E

D I G I T A L C I R C U I T S E E D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,

More information

Code No: 07A3EC03 Set No. 1

Code No: 07A3EC03 Set No. 1 Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,

More information

GATE CSE. GATE CSE Book. November 2016 GATE CSE

GATE CSE. GATE CSE Book. November 2016 GATE CSE GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500 043 COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad - 500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science

More information

Logic design Ibn Al Haitham collage /Computer science Eng. Sameer

Logic design Ibn Al Haitham collage /Computer science Eng. Sameer DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as

More information

Computer Architecture and Organization:

Computer Architecture and Organization: Computer Architecture and Organization: Introductory lecture By: A. H. Abdul Hafez abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com 1 Outlines 1. What is computer? 2. What is this course looking at? Computer

More information

Class: S.E. (Electrical) Course: 2012 PAT. Semester: IV : FUNDAMENTALS OF MICROPROCESSOR AND MICROCONTROLLER Textbooks:

Class: S.E. (Electrical) Course: 2012 PAT. Semester: IV : FUNDAMENTALS OF MICROPROCESSOR AND MICROCONTROLLER Textbooks: Jagdamba Education Society s S.N.D. COLLEGE OF ENGINEERING & RESEARCH CENTRE Tal: Yeola Dist: Nashik Department of Electrical Engineering Academic Year: 2013-2014 (Teaching Plan) Class: S.E. (Electrical)

More information

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF COMPUTING DEPARTMENT OF CSE COURSE PLAN

SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF COMPUTING DEPARTMENT OF CSE COURSE PLAN SRM UNIVERSITY FACULTY OF ENGINEERING AND TECHNOLOGY SCHOOL OF COMPUTING DEPARTMENT OF CSE COURSE PLAN Course Code : CS0205 Course Title : MICROPROCESSOR & INTERFACING Semester : III Course Time : JULY

More information

10EC33: DIGITAL ELECTRONICS QUESTION BANK

10EC33: DIGITAL ELECTRONICS QUESTION BANK 10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function

More information

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY

DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many

More information

5. (a) What is secondary storage? How does it differ from a primary storage? (b) Explain the functions of (i) cache memory (ii) Register

5. (a) What is secondary storage? How does it differ from a primary storage? (b) Explain the functions of (i) cache memory (ii) Register General Concepts 1. (a) What are combinational circuits? (b) Perform the following: (i) Convert (0.5625) 10 = ( ) 2 (ii) (010010) 2 (100011) 2 = ( ) 2 2. (a) Using truth table prove that A B= A+ B (b)

More information

Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING. Fifth Semester. Subject: VHDL Programming

Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING. Fifth Semester. Subject: VHDL Programming Department of Technical Education DIPLOMA COURSE IN ELECTRONICS AND COMMUNICATION ENGINEERING Fifth Semester Subject: VHDL Programming Contact Hours/Week : 04 Contact Hours/Semester : 64 CONTENTS No. Of

More information

Computer Architecture: Part V. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Computer Architecture: Part V. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Computer Architecture: Part V First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Addition and Subtraction Multiplication Algorithm Array Multiplier Peripheral

More information

CS303 LOGIC DESIGN FINAL EXAM

CS303 LOGIC DESIGN FINAL EXAM JANUARY 2017. CS303 LOGIC DESIGN FINAL EXAM STUDENT NAME & ID: DATE: Instructions: Examination time: 100 min. Write your name and student number in the space provided above. This examination is closed

More information

SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR

SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207-208) Course / Branch : M.Sc CS Total Hours : 45 Subject Name : Computer Networks

More information

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system?

MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s. 2. Why the decimal number system is also called as positional number system? MGU-BCA-205- Second Sem- Core VI- Fundamentals of Digital Systems- MCQ s Unit-1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the

More information

DIRECTORATE OF DISTANCE EDUCATION COMPUTER ORGANIZATION AND ARCHITECTURE/INTRODUCTION TO COMPUTER ORGANIZATION AND ARCHITECTURE

DIRECTORATE OF DISTANCE EDUCATION COMPUTER ORGANIZATION AND ARCHITECTURE/INTRODUCTION TO COMPUTER ORGANIZATION AND ARCHITECTURE www.lpude.in DIRECTORATE OF DISTANCE EDUCATION COMPUTER ORGANIZATION AND ARCHITECTURE/INTRODUCTION TO COMPUTER ORGANIZATION AND ARCHITECTURE Copyright 2012 Lovely Professional University All rights reserved

More information

EE 3170 Microcontroller Applications

EE 3170 Microcontroller Applications EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline

More information

UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination

More information

Chapter 4. Combinational Logic

Chapter 4. Combinational Logic Chapter 4. Combinational Logic Tong In Oh 1 4.1 Introduction Combinational logic: Logic gates Output determined from only the present combination of inputs Specified by a set of Boolean functions Sequential

More information

Department of Computer Science University of Peshawar UNDERGTRADUATE CURRICULUM BCS

Department of Computer Science University of Peshawar UNDERGTRADUATE CURRICULUM BCS Department of Computer Science University of Peshawar UNDERGTRADUATE CURRICULUM BCS Code: BCS231 Credit Hours: 3 Digital Logic Design Numbering Systems a) Number Representation, Conversion, and Arithmetic

More information

Final Exam Review. b) Using only algebra, prove or disprove the following:

Final Exam Review. b) Using only algebra, prove or disprove the following: EE 254 Final Exam Review 1. The final exam is open book and open notes. It will be made up of problems similar to those on the previous 3 hour exams. For review, be sure that you can work all of the problems

More information

COURSE STRUCTURE AND SYLLABUS APPROVED IN THE BOARD OF STUDIES MEETING HELD ON JULY TO BE EFFECTIVE FROM THE ACADEMIC YEAR

COURSE STRUCTURE AND SYLLABUS APPROVED IN THE BOARD OF STUDIES MEETING HELD ON JULY TO BE EFFECTIVE FROM THE ACADEMIC YEAR COURSE STRUCTURE AND SYLLABUS APPROVED IN THE BOARD OF STUDIES MEETING HELD ON JULY- 2000 TO BE EFFECTIVE FROM THE ACADEMIC YEAR 2000-2001 MCA SEMESTER -1 Scheme of evaluation Max. Marks Min. Marks to

More information

FUNDAMENTALS OF DIGITAL CIRCUITS

FUNDAMENTALS OF DIGITAL CIRCUITS FUNDAMENTALS OF DIGITAL CIRCUITS THIRD EDITION A. Anand Kumar Principal K.L. University College of Engineering K.L. University Green Fields, Vaddeswaram Guntur District Andhra Pradesh Delhi-110092 2014

More information

Rewa Engineering College, Rewa. Rewa Department OF Electrical Engineering

Rewa Engineering College, Rewa. Rewa Department OF Electrical Engineering Rewa Engineering College, Rewa Rewa 486001 Department OF Electrical Engineering VI TH SEMESTER Microprocessors and Microcontrollers SESSION: 2017-18 Prepared by: Durgesh Choudhary Approved by H.O.D. 1

More information

Computer Logical Organization Tutorial

Computer Logical Organization Tutorial Computer Logical Organization Tutorial COMPUTER LOGICAL ORGANIZATION TUTORIAL Simply Easy Learning by tutorialspoint.com tutorialspoint.com i ABOUT THE TUTORIAL Computer Logical Organization Tutorial Computer

More information

COMBINATIONAL LOGIC CIRCUITS

COMBINATIONAL LOGIC CIRCUITS COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic

More information

BCS Higher Education Qualifications. Level 4 Certificate in IT. Computer Network Technology Syllabus

BCS Higher Education Qualifications. Level 4 Certificate in IT. Computer Network Technology Syllabus BCS Higher Education Qualifications Level 4 Certificate in IT Computer Network Technology Syllabus Version 4.0 December 2016 This is a United Kingdom government regulated qualification which is administered

More information

Guru Jambheshwar University of Science & Technology, Hisar Scheme for Theory + Practical Based Subjects

Guru Jambheshwar University of Science & Technology, Hisar Scheme for Theory + Practical Based Subjects Guru Jambheshwar University of Science & Technology, Hisar Scheme for Theory + Practical Based Subjects Guidelines for Scheme of examination of UG Course Computer Science-B.A. Pass course (under semester

More information

Department Computer Science

Department Computer Science Department Computer Science PROGRAMME OUTCOMES OF B.SC. PROGRAMMES Apply the broaden and in-depth knowledge of science and computing to analyse, think creatively and generate solutions to face the global

More information

Question Total Possible Test Score Total 100

Question Total Possible Test Score Total 100 Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,

More information

Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits

Course Batch Semester Subject Code Subject Name. B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits Course Batch Semester Subject Code Subject Name B.E-Marine Engineering B.E- ME-16 III UBEE307 Integrated Circuits Part-A 1 Define De-Morgan's theorem. 2 Convert the following hexadecimal number to decimal

More information