Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore

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2 COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman Honorary Professor Supercomputer Education and Research Centre Indian Institute of Science, Bangalore T. Radhakrishnan Professor of Computer Science and Software Engineering Concordia University Montreal, Canada Delhi

3 COMPUTER ORGANIZATION AND ARCHITECTURE V. Rajaraman and T. Radhakrishnan 2007 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN The export rights of this book are vested solely with the publisher. Fourth Printing July, 2011 Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111, Patparganj Industrial Estate, Delhi and Printed by Rajkamal Electric Press, Plot No. 2, Phase IV, HSIDC, Kundli , Sonepat, Haryana.

4 CONTENTS Preface xi 1. Computer Systems A Perspective 1 13 Learning Objectives Introduction A Programmer s View of a Computer System Hardware Designer s View of a Computer System Objectives of the Computer Architect Some Invariant Principles in Computer design 9 Summary 11 Exercises Data Representation Learning Objectives Introduction Numbering Systems Decimal to Binary Conversion Binary Coded Decimal Numbers Weighted Codes Self-Complementing Codes Cyclic Codes Error Detecting Codes Error Correcting Codes Hamming Code for Error Correction Alphanumeric Codes ASCII Code Indian Script Code for Information Interchange (ISCII) 34 Summary 35 Exercises 37 iii

5 iv 3. Basics of Digital Systems Learning Objectives Boolean Algebra Postulates of Boolean Algebra Basic Theorems of Boolean Algebra Duality Principle Theorems Boolean Functions and Truth Tables Canonical Forms for Boolean Functions Binary Operators and Logic Gates Simplifying Boolean Expressions Veitch Karnaugh Map Method Four-Variable Karnaugh Map NAND and NOR Gates Design of Combinatorial Circuits with Multiplexers Programmable Logic Devices Realization with FPLAs Realization with PALs Sequential Switching Circuits A Basic Sequential Circuit Flip-Flops Counters A Binary Counter Synchronous Binary Counter Shift Registers 88 Summary 92 Exercises Arithmetic and Logic Unit I Learning Objectives Introduction Binary Addition Binary Subtraction Complement Representation of Numbers Addition/Subtraction of Numbers in 1 s Complement Notation Addition/Subtraction of Numbers in Two s Complement Notation Binary Multiplication Multiplication of Signed Numbers Binary Division Integer Representation Floating Point Representation of Numbers Binary Floating Point Numbers IEEE Standard Floating Point Representation 123

6 v 4.12 Floating Point Addition/Subtraction Floating Point Multiplication Floating Point Division Floating Point Arithmetic Operations Logic Circuits for Addition/Subtraction Half and Full-Adder Using Gates A Four-bit Adder MSI Arithmetic Logic Unit A Combinatorial Circuit for Multiplication 142 Summary 143 Exercises Arithmetic Logic Unit II Learning Objectives Introduction Algorithmic State Machine Algorithmic Representation of ASM Charts Designing Digital Systems Using ASM Chart Floating Point Adder 165 Summary 168 Exercises Basic Computer Organization Learning Objectives Introduction Memory Organization of SMAC Instruction and Data Representation of SMAC Input/Output for SMAC Instruction Set of SMAC Instruction Set S1 of SMAC Instruction Formats of SMAC Assembling the Program into Machine Language Format Simulation of SMAC Program Execution and Tracing Expanding the Instruction Set Vector Operations and Indexing Stacks Modular Organization and Developing Large Programs Enhanced Architecture SMAC Modifications in the Instruction Formats for SMAC SMAC++ in a Nutshell 200 Summary 201 Exercises 202

7 vi 7. Central Processing Unit Learning Objectives Introduction Operation Code Encoding and Decoding Instruction Set and Instruction Formats Instruction Set Instruction Format Addressing Modes Base Addressing Segment Addressing PC Relative Addressing Indirect Addressing How to Encode Various Addressing Modes Register Sets Clocks and Timing CPU Buses Dataflow, Data Paths and Microprogramming Control Flow Summary of CPU Organization 236 Summary 238 Exercises Assembly Language Level View of Computer System Learning Objectives Introduction Registers and Memory Instructions and Data Creating a Small Program Allocating Memory for Data Storage Using the Debugger to Examine the of Registers and Memory Hardware Features to Manipulate Arrays of Data Stacks and Subroutines Arithmetic Instructions Bit Oriented Instructions Input and Output Macros in Assembly Language Instruction Set View of Computer Organization Architecture and Instruction Set 269 Summary 271 Exercises 271

8 vii 9. Memory Organization Learning Objectives Introduction Memory Parameters Semiconductor Memory Cell Dynamic Memory Cell Static Memory Cell Writing Data in Memory Cell Reading the of Cell IC Chips for Organization of RAMs D Organization of Semiconductor Memory D Organization of Memory Systems Dynamic Random Access Memory Error Detection and Correction in Memories Read Only Memory Dual-Ported RAM 293 Summary 294 Exercises Cache and Virtual Memory Learning Objectives Introduction Enhancing Speed and Capacity of Memories Program Behaviour and Locality Principle A Two-Level Hierarchy of Memories Cache Memory Organization Design and Performance of Cache Memory System Virtual Memory Another Level in Hierarchy Address Translation How to Make Address Translation Faster Page Table Size Page Replacement Policies Page Fetching Page Size Combined Operation of Cache and Virtual Memory 327 Summary 328 Exercises Input-Output Organization Learning Objectives Introduction Device Interfacing Overview of I/O Methods 336

9 viii 11.4 Program Controlled Data Transfer Interrupt Structures Single Level Interrupt Processing Handling Multiple Interrupts Interrupt Controlled Data Transfer Software Polling Bus Arbitration Daisy Chaining Vectored Interrupts Multiple Interrupt Lines VLSI Chip Interrupt Controller Programmable Peripheral Interface Unit DMA Based Data Transfer Input-Output (I/O) Processors Bus Structure Structure of a Bus Types of Bus Bus Transaction Type Timings of Bus Transactions Bus Arbitration Some Standard Buses Serial Data Communication Asynchronous Serial Data Communication Asynchronous Communication Interface Adapter (ACIA) Digital Modems Local Area Networks Ethernet Local Area Network Bus Topology Ethernet Using Star Topology Wireless LAN Client-Server Computing Using LAN 375 Summary 376 Exercises Advanced Processor Architectures Learning Objectives Introduction General Principles Governing the Design of Processor Architecture Main Determinants in Designing Processor Architecture General Principles Modern Methodology of Design Overall Performance of a Computer System History of Evolution of CPUs RISC Processors 395

10 ix 12.5 Pipelining Instruction Pipelining in RISC Delay in Pipeline Execution Delay due to Resource Constraints Delay due to Data Dependency Pipeline Delay due to Branch Instructions Hardware Modification to reduce Delay due to Branches Software Method to reduce Delay due to Branches Difficulties in Pipelining Superscalar Processors Very Long Instruction Word (VLIW) Processor Some Example Commercial Processors Power PC Pentium Processor IA-64 Processor Architecture 423 Summary 425 Exercises Parallel Computers Learning Objectives Introduction Classification of Parallel Computers Flynn s Classification Coupling between Processing Elements Classification Based on Mode of Accessing Memory Classification Based on Grain Size Vector Computers Array Processors Shared Memory Parallel Computers Synchronization of Processes in Shared Memory Computers Shared Bus Architecture Cache Coherence in Shared Bus Multiprocessor State Transition Diagram for MESI Protocol A Commercial Shared Bus Parallel Computer Shared Memory Parallel Computer Using an Interconnection Network Distributed Shared Memory Parallel Computers Message Passing Parallel Computers Cluster of Workstations Comparison of Parallel Computers 466 Summary 468 Exercises 470

11 Computer Organization And Architecture Publisher : PHI Learning ISBN : Author : V Rajaraman And T Radhakrishnan Type the URL : Get this ebook

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